First custom STM32 board - is this ready to send for fab or am I missing something?

The main issue when you're dealing with high-speed clocks and complex microcontrollers isn't always the component itself, but the impedance on the traces leading to and from those pins. Moving your oscillators to the bottom layer helps keep the routing clean, but if that move pushed them far away from the required ground and power pins, you are likely seeing clock signal integrity issues down the road. For most standard series, the physical distance from the crystal to the VCC/GND pins is critical for maintaining a clean signal and preventing jitter, which can cause boot failures or strange behavior that looks like a wiring mistake.

Regarding your ground plane choices, going with a solid ground pour on both layers is definitly the superior approach for a board running an STM32. You want that ground plane to be as uninterrupted as possable, especally under the power supply section and around the clock circuitry. Stitching is good practice, but if you are using a multi-layer board, maintaining a continuous copper reference plane across both sides helps manage return currents and minimizes noise coupling between your high-speed digital lines and the sensitive analog rails. Cost concerns are valid, and it's smart to review a design before committing to a full run of expensive silicon. However, the biggest risk isn't usally the cost of the main chip failing, but rather the cost of a board that draws excessive current or runs so poorly that it can't even complete its initial startup sequence. Double-check your power sequence diagram against the chip datasheet. It's not enough just to provide power; you need to ensure all voltage rails stabilize and are energized in the exact order the datasheet requires before the microcontroller attempts to execute the reset routine.

If the physical layout constraints truly prevent the ideal crystal proximity, try to utilize short, wide traces to connect the crystal pins to thier nearest power and ground vias. Shorter and wider is always better to reduce inductance and parasitic noise, regardless of what the datasheet suggests as a minimum requirement.

I totally agree with the point about keeping the ground plane solid across both layers. It makes a huge difference. When I did some work on a sensitive data logger, I noticed that even if the traces looked fine, any big gaps or breaks in that ground pour acted like little antennas that picked up noise. Just keeping it uninterrupted made the sensor readings much cleaner and more reliable in the field.

I worry about that crystal placement too, but sometimes the biggest issues are right at the pins. It's not just the crystal itself, but the decoupling caps right next to the chip. I spent a ton of time researching chipsets until I found a specific set of ceramic capacitors with extremely low ESR. Once I switched to those, my power rails finally settled down and my boards stopped randomly resetting during boot. A good decoupling setup keeps the signal clean even if the routing isn't absolutely perfect. If you're worried about the cost, remember that testing isn't just about power up. Those few bucks spent on a few extra capacitors or even a slightly beefier board stack might save you a huge headache down the line when the chip behaves weirdly under load.