Marc,
See my other postings. Only trying to make one simple point here.
As Paul points out (correctly), the tools try to fit generic HDL into the special structures (or else why would we even try to put them in).
Often the tools can't make the best, and most clever use of the device specific features, until a number of years have gone by, and the tools have been improved to that point.
After a number of years, we (as FPGA IC designers) are onto the generation after the next generation ....
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