Pcb questions

BTW, in exporting the board outline it has the rout tool diameter. Surely when cutting they automatically adjust the edge for there size? How am I suppose to know their tool diameter? It seems it would be easier for them simply to offset the tool to half the diameter? This seems important because your board can get cut to much if not ;/

Oh, and the offset of the route is different. When I created the pcb I offset the entire board(changed the origin) several inches since I didn't like it hugging the corners. Is this a problem? Will they automaticaly position everything for optimal cutting or do I need to shift the board to 0 coordinate?

Any coordinate is ok - they will sort that. For routing profile, it is usual to create that on mechanical layer1. When plotting, I have the choice of 'include mech1 on all layers'- I say 'NO'. They will use the mech 1 as their routing profile ( separate front end job) as it has the same 0,0 reference as the rest of your layers, everything will line up. Forget tool radius offsets, that's their choice. They will route to the inside edge of mech1, and make the appropriate offset, depending on their router size... Where you DO have to take this into account, is when you pannelise using a rout as opposed to score.You will need to know the offset between panels, and that will depend on what size router the manufacturer choses. Usually this wil be 1.6mm. Another consideration for router size, is inside corners. Can you tolerate a

0.8mm rad ? Most can, some will not, so a smaller router has to be specified. That would IMO be a poor design, as it reqires the manufacturer to use 'non preferred' router sizes.

In my EDA the default rout tool dia is 200mils ;/ Seems kind large. (yes, they say rout which I guess is a typo).

Strange ;/ I opened one of the gerber layers in pentalogix viewmate and it's got some problems ;/ some text is screwed up and a pad is missing. Looks find in camtastic.

I put the board outline on the drill drawing (could be a fab drawing) layer. This is supplied as a Gerber and a PDF. The drill drawing layer also has the dimensions of the board. If it's a complex shape, I'll supply a normal 2D drawing showing outline dimensioning and a DXF file of the outline. For panelized boards, I supply a drawing of the panel, complete with fiducial locations on the panel edge, and a DXF file with just the routing information. You can't use the plane extents as the board outline as the plane normally stops short of the edge of the board by 20mils or more. If they second guessed your board outline, they would have added 40 to 100 mils to your board size to bring it in line with normal PCB practices.

The board house needs to have all information. They will not second guess what you want.

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Mark

You should have.

By far the easiest and least confusing thing to do is simply create a board outline on one of the machnical layers that gets exported as another gerber layer. That way they know exactly were to route, exactly what the dimensions are

9you don't need to tell them), and a have reference point in the gerber so it all lines up. No mess, no fuss, no questions.

Hopefully? If you can't get the outline right, how did you expect them to?

Simply tell them you want tented vias (covered in solder mask). But ultimately your solder mask gerber should show exactly what you want and just tell them to follow your gerber. I don't know why they asked this, they usually just follow your gerber, something must seem unusual to them.

Dave.

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Gerber files don't inherently include board size/shape information.

In Protel, I place a very thin track (5 mil or so) on a mechanical layer, and include that layer on all Gerbers. In my readme file, I state that the boards should be trimmed to the outline on all layers (or do I say "top layer" - whatever, it works.

There may be a padstack definition problem. Use a Gerber viewer to see if the generated Gerbers really have all the information that you require. If the 26 mil holes are vias, you probably don't need a solder mask pad on them (but Protel generates solder mask pads on vias for me, so the board shop may expect them.)

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Peter Bennett, VE7CEI  
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Surely=20

=20

them=20

because=20

It reflects the assumption made in the path calculation. (in the file)

didn't=20

to 0=20

I would expect that they will take care of this since the offset is = readily visible.