Stupid question

Is there a better Verilog sequence for the polynomial-multiplier

begin C[10:0]

Reply to
Thomas Womack
Loading thread data ...

I really don't think you mean quite that. Maybe if the assignments were blocking, instead? (always assuming you're trying to do the whole thing in one clock cycle)

This sounds a bit nicer... it depends on the fact that XORing with zero has no effect. Some details missing, of course.

reg [20:0] C; reg [10:0] A, B; integer i; ... C = 0; for (i=0; i

Reply to
Jonathan Bromley

If you just want to avoid the manual replication in the concatenated vector, use the replicate {{ }}:

C[10:0] begin

Reply to
John_H

Reply to
Petter Gustad

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.