I know it compresses the bitsream based on the unused slices in the design. But how exactly it work? Does the Xilinx Spartan 3 FPGA automatically understand this compressed bitstream (may be though some bitfile header settings)? If it really does, then why we dont have it as default? whether it saves 5% or 10% if there is no price to pay (like some decompression logic that u save if you dont used compressed option) why not all the people use it?
~Naveen