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why does speed grade effect VHDL program??

Hey

Quartus automatically during compile promotes the CLK signal to a global. I tried manually doing it where you instructed and its not as you describe. I have quartus II 5.0. I have the design working with both the -10 and -15 part now. I would probably be more cautious with timing if the output wasnt going to a bank of LEDs. If it glitches every so often, it will be undifferentiated by a human right?? I dont see any glitches or issues with the system running right now. Now when it comes time to do the 32 buttons, I might be in for trouble, although it worked when it was breadboarded too.

Thanks matt

Reply to
Matt Clement
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Hi,

  1. My bad. You should put "CLK" in the To name, not the From name.

  1. You open the assignment editor by typing Ctrl-Shift-A. I have v5.1, but I don't think the keyboard shortcut has changed.

  2. At the top, make sure that the "All" or "Logic Options" filter is selected. I think it defaults to "Pin" the first time you open the editor.

How are you generating the clock for the data? If you're bit-banging, that'll be a real headache to deal with...it's better to generate a strobe or some kind of asynchronous data valid signal.

Cheers.

Reply to
ernie

Thomas gave the answer to the problem. David second it. Why not just adding two flops at sel and add? This will solve the problem.

Reply to
why_don't_you_listen?

Well, I think David gave the answer, and he didn't suggest 'just adding two flops on sel and add'. He correctly pointed out that this won't work, and you need a separate strobe synchronised by flops. HTH, Syms.

Reply to
Symon

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