Hi folks, I want to learn Hardware Verification Language (HVL). Which HVL is the most popular for FPGA design? I have seen "e" and "Open Vera" from Samir Palnitkar and Janick Bergeron books. Are there other Hardware Verification Languages? Say I designed something in FPGA with Verilog or VHDL. How do I know that it is time to verify my design with HVL as opposed to Verilog/VHDL testbenches?
Hendra
You could also look here :
-jg
Cheers, JonB
Hendra, Both VHDL (vhdl-200x) and Verilog (SystemVerilog) are being extended to include HVL constructs. For education, either e or Vera would be ok, but perhaps long term we can be back at one language for all of the design (be it your choice of VHDL or Verilog).
Cheers, Jim
Hendra Gunawan wrote:
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