Hi folks, I want to learn Hardware Verification Language (HVL). Which HVL is the most popular for FPGA design? I have seen "e" and "Open Vera" from Samir Palnitkar and Janick Bergeron books. Are there other Hardware Verification Languages? Say I designed something in FPGA with Verilog or VHDL. How do I know that it is time to verify my design with HVL as opposed to Verilog/VHDL testbenches?
Hendra