Which HVL is the most popular?

Hi folks, I want to learn Hardware Verification Language (HVL). Which HVL is the most popular for FPGA design? I have seen "e" and "Open Vera" from Samir Palnitkar and Janick Bergeron books. Are there other Hardware Verification Languages? Say I designed something in FPGA with Verilog or VHDL. How do I know that it is time to verify my design with HVL as opposed to Verilog/VHDL testbenches?

Hendra

Reply to
Hendra Gunawan
Loading thread data ...

You could also look here :

formatting link

-jg

Reply to
Jim Granville

formatting link

Cheers, JonB

Reply to
Jon Beniston

Hendra, Both VHDL (vhdl-200x) and Verilog (SystemVerilog) are being extended to include HVL constructs. For education, either e or Vera would be ok, but perhaps long term we can be back at one language for all of the design (be it your choice of VHDL or Verilog).

Cheers, Jim

Hendra Gunawan wrote:

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
 Click to see the full signature
Reply to
Jim Lewis

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.