VirtexII-Pro MGT: 8/10 coding bypass problems

Couple of questions to start off with... What's your receiver? If you're receiving into another MGT in the same chip, does it use the same or independant clocking resources?

My guess is that you're exceeding jitter tolerance or frequency accuracy somewhere. The REFCLK tolerance is pretty tight,

--Josh

Currently I am receiving onto another MGT on the same chip and clocked by the same reference clock. The clock that I am using is rated as

50MHz with stability of +/-50ppm. This should give about 2ps of jitter which is way below the spec of 50ps.

Is it possible for noise on the power supply to have such a large influence? I will try again with a higher quality power supply and see what comes up.

--Herwin

I'd expect the bypassing on the board would be more important than the actual power supply.

-- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.

Howdy Herwin,

I'm not sure what serial bypass mode is - did you mean 8b/10b bypass?

What are your results using serial loopback? How about parallel loopback? If either has trouble, focus on that before trying to traverse the PCB (remeber that serial loopback still requires terminations on the _tx_ interface). Also, with a 50 MHz clock, I assume you have SERDES_10B set to its default "FALSE".

The CDR in the Rocket I/O can handle at least 75 consecutive identical digits, so at least by itself, I doubt that is your problem. But, if you had termination problems, I could maybe see how consecutive digits might influence BER like you have.

As the other responder mentioned, the jitter requirements are a little on the tight side. Another thing that could really throw a wrench into the situation is using a PLL-based clock as the reference - some fanout buffers, especially zero delay ones, use PLL's. Where is the reference clock coming from (including the original source, through what device(s), into which pin, and across what nets on the FPGA)?

Good luck,

Marc

Herwin -

+/-50ppm is an accuracy rating and has nothing to do with jitter. You'll have more than 2ps of jitter on that clock by the time it hits the MGT. Not saying jitter is your problem, just pointing out that you may want to take a closer look at it.

Rob

The system runs with 8/10 bypass, and the tests that I performed used the serial loopback mode. Parallel loopback works perfectly. The clock that I am using is directly from a crystal oscillator from Sunstu (SOVB25T). Indeed, I am now suspecting that the jitter requirement has been violated. I am now trying to investigate what this jitter is on this part.

As for how the reference clock is routed: The signal is first fed through an input buffer. The output net is connect to both a DCM (for the logic) and the MGT reference clock input.

Thanks a lot for the feed back

Herwin