VHDL State Machine - Literature

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Where is a good place to find info on building VHDL moore FSMs? I am trying
to design a vending machine with the following features on a spartan 3
It has the following features:
1) 5 products price - 55/60/65/70/75c
2) 3 different coin inputs -25 c/10c/5c
3) Need to display the product price and price entered via the 3 coin
inputs.(first 2 digits display coin input values, last 2 digits display
product price, use any digits to display change out)
4) When the value of product selected is reached, it should be dispensed
and any change displayed.
5) System should reset after this and also reset if done asynchronously.

The books I have talk about FSMs for 4-5 pages. Not good enough for me to
start thinking about this the right way.

Re: VHDL State Machine - Literature


There is a short presentation on modeling
synchronous edge triggered FSMs in Verilog, at:

The VHDL syntax will be different, but the
modeling techniques are the same.

Hope that helps,

fpgawizz wrote:
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