I have a memory that output a 64-bit slv. I have another module that has a record type with a data 64-bit slv input. I want to connect the two together. If I do this I get x. If I disconnect them the mem outputs what I expect. I can also connect a constant to the record and see that value. Not sure why I cant connect the two as I get no errors in modelsim.
TIA
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a
I
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Which tool is giving the problem?
Some synthesizers misinterpret your intentions unless you assign all of a signal in one concurrent assignment statement (that is, not in an explicit process).
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X means you have 2 or more active driver on a signal driving different values. Replace the std_logic_vector by std_ulogic_vector to detect in compile time your problem. Modelsim can't throw error, as your code is legal vhdl according to lrm (but most likely useless/not what you like to get) and modelsim simulates it correct.
bye Thomas
Thanks for the help. I actually had something else driving the signal.
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