Hi everyone, I have recently purchased a XC3S200 based board with 256KB Flash, 256KB platform flash and 32KB SRAM. So out of my interests I figured I would design a simple SoC as a learning excercise. I have designed a VGA framebuffer which does 640x480 (but uses pixel doubling so 320x240x2-bit). A complete framebuffer is ~19KB.
At this point I decided I would have to read the framebuffer at a line at a time. A scanline in this mode would need 80 bytes of memory.
Naturally I decided to infer a block RAM with 8-bit data width (well9-bit, but I am not using parity).
The problem though is that when the Block RAM is 8-bits, you get almost2KB of space!! So that means I am wasting more than 90% of the space!!
I was looking into using a 8 128x1 distributed RAM and wire them in a way to extend the data word to 8-bits. I am not certain how much of my logic resources this would eat up.
I am fairly new to the FPGA's so I'm not certain if these are the best methods to buffer such a small amount of memory. What would you do if you were in my situation?