It's possible to add a diode or two so that the large scale ramp during turn on is slowed down, but the small scale perturbations (less than a diode drop) aren't affected.
These days it's better to get one with built in soft start.
A lot of linear regs have 'ref' pins, which can be used to slow the rise time without affecting the closed loop response.
Regards, Allan
Austin,
No need to worry. The boys here have been designing drives since the early 80s. Most are MIT grads. Also we set up motors and drives and run them fairly hard and continuously for months.
Dave Colson
Vaughn,
Only 5.3 amperes surge? How do you test for it? Can you guarantee it? Do you throw away the ones that don't pass? Why was the initial surge set at 20 amperes, and then dropped to 16 amperes, and now down to 5.3 amperes for the 180?
Did you fix the silicon, or figure out how to control the turn on of the power supplies, or measure it, and get a more agreeable number?
Too bad, though. The LX200 is 3.3 amperes, worst case - leakage only, at
85C. Typical is 1.3 amperes at 85C. No start up surge to worry about. And the LX200 is a lot more memory, LUTs and FFs than the EP2S180...Why is it so much worse than Stratix 1? (both surge and leakage)
Is Cyclone 2 just as bad as S2?
Austin
Vaughn Betz wrote:
Aust> Vaughn,
Hmmm... When will we see the first thermal-runaway failures of FPGAs ? Could be time to start teaching thermal-runaway again in the classes, ( and the data sheets... ) and perhaps the tools should perform some 'thermal spreading' to prevent hot spots (since thermal effects are non linear, and one can easily get an additional 40-50'C die above case ).
-jg
Jim,
I did comment.
My numbers were for 85C typical and worst case.
Aust> > Vaughn Betz wrote:
Austin,
I don't know where you're getting these surge numbers from. To my knowledge Altera never quoted surge currents that high for 2S180s.
The TI App note you quoted appears to be a miscommunication, since those numbers are much too high to be either surge or leakage currents.
Altera's power tools take leakage into account in the power-up current they display. So the 1.8 A to 5.3 A of ICC Inrush current is the total current needed to power up the device, including both leakage and any surge current.
The 5.3 A value is power-up current for worst-case silicon characteristics, at 85 C. Is your 3.3 A leakage number for the worst-case power process corner silicon at 85 C, or just typical or unspecified silicon at 85 C? The difference is significant. Leakage increases as threshold voltage drops (or channel length decreases, etc.), so we have provided numbers for both typical process and the highest power units.
Vaughn Altera v b e t z (at) altera.com [remove spaces and use proper @ to reach me]
the
Power
Analyzer
me]
Vaugn,
See below,
Austin
-snip-
Bellnix Power supply guide, TI power supply guide, ST power supply guide...basically your power supply parnters. So, all I can conclude is that Altera told their power vendors what the start up surge was.
...
all state 16 amperes. So if you didn't tell them, who did? If I am an engineer, and I need to design a power system, I would be using these guidelines.
Very effective miscommunication there. Better go talk to all your power vendors and let them know that they all quoted the wrong numbers. I have supplied you with the list above, so you're welcome.
I could understand if your had an early ES version of the part, and perhaps this high current surge was due to fault on an errate sheet, but the 2S180 isn't sampling yet. Maybe this was based on an extrapolation of the 2S60?
So, is there a surge, or no? You imply that all that is needed is the leakage to be overcome (just like our parts since Virtex II). Even your spreadsheet mentions the word "inrush" (6, 1 and 2 amperes for the three supplies). The IO and PD supplies need 8 mA and 15 mA respectively (idle) so why do they need 1 and 2 amperes to start up? I think that is called a Power On Surge (POS)?
That is as it should be. Everyone here does like your power spreadsheet, it has nice formatting, and a clean look. It does have some buggy pop-up windows that tend to stick around and annoy, but otherwise it is a really good and useful spreadsheet tool. Now the only question is: is it accurate?
Yes, it is.
or just typical or unspecified silicon at 85 C?
No, it is not.
The
And so did I.
Interesting you bring this up. A customer demanded to see proof of our LX60 leakage numbers, as they had designed in the 2S60.
They frankly could not belive the numbers. All of the 90nm products they were familiar with had horrible leakage. When we told them that we used a triple oxide technology, and that is how we controlled the leakage, they basically still couldn't believe it.
When we not only provided them with parts and demo boards, and characterization data on leakage, they decided they had to switch to the lower leakage power product.
Vaughn,
And:
For yet another power vendor who just got those darned numbers wrong.
Aust> Vaugn,
OK. Having used so many smaller parts in the past, I still have a hard time not thinking of the XC3S1000 and XC3S1500 as "large".
I think this question is more about the worse noise margin of low-voltage devices than thier MTBF. I've heard the same question being asked by designers of military products of 1.5V FPGAs like the V2Pro. Any info?
-Jim
Jim,
I'll put a new title on this.
The internal logic is running off a lower voltage, so yes, it must manifest itself in some fashion.
How it makes itself known is that with 100 mV of ground bounce, you now have more jitter internal to the core than you would have had with 100 mV on a higher voltage core device.
More jitter means that the timing margins may have to be larger (more slack), or you have to manage the ground bounce, clock jitter, etc. to a greater extent than you may have had to in the past.
This is a major headache, as the speed of the devices only gets faster, yet the jitter (may) get larger -- the two are incompatible!
A great deal of design work is going into the management of jitter in our devices (ie differential clock trees), as well as prediction of jitter for a given application (software tools).
Right now, the only way to guess at how much jitter will be present is to assume a worst case asynchronous multi-clock design environment with less than "best practices" bypassing, and IO's operating at the SSO limits. This worst case assumption leads to numbers that may be far too conservative for your application (but at least we errored on the side of caution, and better performance is achievable).
Use of LVDS IO's, synchronous clock domains, switching some logic on altenate clock phases, best bypassing and decoupling practices, etc. are all able to provide even better jitter numbers than the worst case ones. Differences of 10:1 from your case to the worst case is not unusual.
Contact your local Xilinx FAE for details and help on the subject of jitter, if you are designing high performance (tightly constrained) FPGAs.
Austin
Jim George wrote:
-snip-
knowledge
The TI and Bellnix app notes list 16 amperes for the 2S180, but don't state that it is surge current, for the simple reason that it is not. The digikey app note does imply this is a power-up current, which is wrong, and we will tell them to fix that.
The current numbers in the app notes are "reasonable worst-case" *total* current draws during operation. That means dynamic power + leakage power, during operation of a high-speed, high-utilization design with a high, but not extreme, switching probability per clock cycle for registers & combinational logic. Dynamic power dominates. Since dynamic power is such a strong function of what you're doing with a device, we recommend that you use the Altera Early Power Estimator, or even better, the Quartus Power Analyzer to get an accurate number for your specific design, as I've previously explained.
The poor communication on our part was that we did not ensure that what the current draws in these app notes represent (reasonable worst-case total power during operation) was well explained. We thought it would be clear that that was the case, but certaintly this exchange shows that it was not clear to you Austin, so we'll make sure the app notes get updated to be as immune to misinterpretation as possible.
Interestingly the equivalent TI app note for Xilinx lists the smaller and slower Virtex2Pro family as requiring up to 10 A of Vccint current. It doesn't say what that current is. I think a good guess would be that it is the "reasonable worst-case" total Vccint current during operation for a large V2Pro device, although it seems your guess would be surge current.
The 2S180 has 1.8X the logic capacity of the largest Virtex2Pro device (the
2VP100). The 2S180 also runs 50% faster, on average. So you get ~2.7X the processing power in the 2S180 that you do in the 2VP100. If I assume that Xilinx and Altera both defined "reasonable worst-case total power" in the same way (a big if, I'll admit), power in the largest V2Pro is 15 W (10 * 1.5) vs. the 19.2 W (16 * 1.2) for the largest Stratix II. So for 26% more power, I get 2.7X the processing power. Put another way, for equivalent processing capability, you only need 46% of the power in Stratix II that you do in V2Pro. This TI app note has no data on Virtex4 power, so I can't compare to Virtex4.characteristics,
How about Vccaux power? The Xilinx web calculator lists a Virtex4 LX200 power on the Vccint supply of 661 mW -- 6X lower than the worst-case, 85 C number. It also lists a Vccaux power of 375 mW -- again typical silicon, 25 C. Is the 85 C, worst-case number 6X larger for that too, so the real leakage power dissipation is 6.2 W when you sum Vccint & Vccaux?
Regards,
Vaughn
Altera
v b e t z (at) altera.com [remove spaces and use proper @ to reach me]
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