The key here is what latency you can withstand and what size you need. For relatively small requires the internal SRAM of FPGAs like Spartan or Cyclon e is fairly fast and cost effective solution. Fot bigger sizes and if you c an accept a little more latency FPGA + SRAM/SDRAM/DDR3 is a good solution. We get a lot of people using our Craignell2 -40/48 parts for this as we 256 Mb of SDRAM paired with a Spartan-3A. The 48 pin part allows a FIFO with 1
6 bit data bus input and with up to 7 control signals and the mirror of tha t on the output. The 40 pin can still do 16 bit data in/out but you can onl y support 3 controls signals.To reduce latency a hybrid structure can be used for a FIFO. This is much m ore complex but gives the bigger size without losing too much performance o n latency. Basically to do this you have an input SRAM in the FPGA and on t he way out an output SRAM. Those give the I/O speed. As appropriate blocks of data are moved in/out of the SDRAM in a background operation. Filling(ou tput) or emptying(input) SRAM elements of the FIFO.
One of the nice things you can do in this sort of FIFO that standard parts can't usually do is differing interface sizes. So you might have an 8 bit w rite with a 32 bit read.
John Adair Enterpoint Ltd.
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