Hi,
ist there any vhdl example published for use of an external SRAM as a dual ported RAM?
I imagine a state machine writing a data flow into the RAM, and a short FIFO for the read path out of the RAM, and some logic feeding the FIFO and handling the arbitration to the RAM. Maybe a write FIFO is also necessary.
The RAM has 512k x 8.
Thanks for any hint.
Klaus Hiltrop
Hi,
I have found this
Christos.
Thank you Christos,
your link finally leads to
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Indeed in my case the incoming (serial) data stream cannot be interrupted and needs to put data into RAM immediately.
Because of the serial-parallel conversion there is time to read data for the other side which wants to get the data out of the RAM, asynchronously to the in-data-stream.
As I cannot preview when the serial stream sends data or stops, I need to fill a FIFO at least for the reading side as long as any data is available in the RAM. writing into RAM and reading from it seems from outside completely asynchronous.
Maybe I will also need a FIFO for the in-data as the routine/state machine filling the read-FIFO cannot know when new data-in comes. There is a sort of arbiter necessary controlling the accesses to the RAM.
A short buffer of this type could be realized inside the FPGA with a dual ported RAM, however 512k Bytes is too much. In order to keep cost of the final product low the external RAM should be a usual single port RAM.
Klaus
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