tricks to make large PLAs fast?

Eric Smith · 2006-02-27T08:08:29+00:00

I have a design with a large PLA, and I'm trying to make it run fast ina Spartan-3. It's too big for block RAM, since it has 25 inputs,slightly fewer than 512 product terms, and 32 outputs.My first attempt was to just translate the PLA equations to VHDL andsynthesize it with the default settings. This uses 34% of a 3S500E, andhas a minimum cycle time of slightly under 12 ns with over 20 levels oflogic. If I turned on timing-directed mapping, or increased the effortlevels, I suppose it might get slightly better. But my own analysissuggests that it should be possible to implement the PLA with no morethan 11 levels of logic worst case, seven levels for the product terms,and 4 levels for the sums.Anyhow, as the subject line suggests, I'm interested in any clevertricks to get more efficient FPGA implementation of the PLA. Forinstance, would use of the carry chain speed up wide gates? (Or dothe tools already infer that?) Should I put some constraint on theproduct terms, to keep the tools from merging the product term andsum logic?I'll experiment with this myself, but perhaps someone here has alreadydone this, in which case suggestions would be quite welcome.Thanks,Eric

Feb 27, 2006 20 Replies

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Eric Smith 20 years ago

Oops, that's what I meant.

Using '-' in a comparison works for synthesis, but not simulation. Now that I'm looking at it again, it looks like using std_match instead of the '=' operator would do what I want.

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