Temperature considerations of inactive logic blocks

You cannot reduce leakage current by changing the bitstream. Peter Alfke

You mean Static leakage, in current Xilinx FPGAs ?

It is not a bad idea, to have as well as Clock Enables and clock distribution management, a similar thing with Core Power ? Other fields do this already to mitigate the power hits of the finer processes, and it would cost a little die area. It would not surprise me to see this on future parts.

Then, the P&R software could have two more targets : Minimum Clocked Power, and minimum Static Power :)

To answer this specific question, you should create two valid designs, and measure them. Depending on where the inactive channel CLOCKs are gated, (and even the physical placements) you could expect to find a power saving.

-jg

I was addressing todat's situation in all FPGAs, since none has Vcc control. In the future one can think of many selective power-down solutions, but they have their own little problems and trade-offs. I just answered an applications question. Peter Alfke