Talk of devices from 1,792 to 15,260 logic blocks, and currents a little under Altera'a MAX IIZ (on a Logic Block basis).
Not stellar Static ICc values, but reasonable - considering they have to fight 65-nm process leakages.
So the logic sounds generic - what about the memory ? Does anyone know the details of the memory technology ?
They seem VERY cagey on the exact memory technology, and do not use the words Reprogramable - but there is mention of "The architecture is said to be scalable to 40-nm and the family is being offered in both volatile and non-volatile memory versions"
and this comment is a little ominous "In our business it is critical to have fast, accurate simulation technology in order to ensure first-pass working devices,"
So it looks like OTP memory loading a SRAM FPGA ?, and the volatile models could either be the largest ones, or ones that failed the OTP tests ?.
OTP is tolerable for config memory, if you can bypass that for development - some CPLDs offer this dual-path already.
Even uC are revisiting OTP (after some claims FLASH was the only path) so there must be price benefits.
If it is OTP, that raises the question of programming yields, and flows.
The FPGA market is not showing strong growth, in fact they vacuum R&D dollars, whilst under-performing the fabless industry averages. Can SiliconBlue hit critical mass ?
-jg