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Same Bitstream: Different Performance

Hello All, Another question for the Gurus. Besides the fact that each device is unique and has a "mind (or body or whatever !) of its own, what do you think could be other possible causes for the same bitstream behaving differently in different devices ? I have a board which has 9 Xilinx V2P7s and all of them are identical in function. I configure all of them with the same configuration file. But when i test them, some of them behave differently than the others.(5 are perfect and 3 have problems, for example). I use all 8 Rocket IOs on each of the 9 devices. My refclk is 80 MHz, userclk is 40 MHz and we are running at 800Mbps on our differential inputs. Our system clock is 40 MHz and so I would like to think that we are not really in the "high speed" domain. I don't see any timing violations. Am I just getting lucky with the 5 devices or unlucky with the 3 ? What are the chances of this being an external problem vis-a-vis and internal one ? We have been in a tough loop for a long time. The board also has, besides the Xilinxs, a couple of Stratix devices, a VME interface, Memories, Transcievers and a few other ICs. So the source of problems could be potentially a lot of things. Any similar experiences/suggestions/solutions ? Thanks in advance, Adarsh

Reply to
Adarsh Kumar Jain
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Sounds like a logic race. Something is not synchronized properly to the system clock.

Synchronization problems rarely show up in simulation or timing analysis.

I expect that the 5 devices will eventually exhibit similar problems over time and temperature. You are lucky that you discovered the problem on the bench.

-- Mike Treseler

Reply to
Mike Treseler

Hi Adarsh, If you are driving either of the Comma Alignment inputs on the MGT, make sure follow the guidelines for phase aligning your signals to the MGT from Chapter 2 of the RocketIO Transceiver user guide (p67 in the version I keep on my desk). In my experience, if the comma align signals are used but not phase aligned correctly, the resulting timing problems can make device behavior change from MGT to MGT.

If you need an example, try downloading the Aurora reference design for Core Generator and take a look at the phase_align module and the corresponding constraints in the ucf file. You can get to it by going to

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If this isn't your problem, you'll probably want to look at all the usual culprits for flaky Transceiver behavior: power supply noise, too much jitter on reference clocks and incorrect coupling/termination. Failing that, you should be on the lookout for accidental asynchronous design.

Regards,

Nigel

Adarsh Kumar Ja> Hello All,

Reply to
nigelg

Xilinx and Stratix on the same board?!?!?? ;)

Reply to
Chris

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