Now I am doing Xilinx Virtex2 (xc2v1000) readback to capture register states. I have some question about it, I hope somebady can help me! Thanks a lot.
- when I only want to read back one frame, for instance, xc2v1000 device,after I specify the frame address in the FAR register, How many frame size (number of word to readback) should I load to FDRO register(only type I )? xc2v1000 has the frame length in bits 3392. If does the readback stream contain one pad frame(3392 bit) prior to the desired readback frame (3392 bit) specified by FAR register? The question is number of frame size ,106 or 212?
2.are there pad words between the readback frames?
- flush the command pipe with 32 bits of zeros. How many times should I do? Because I have read the Virtex2 platform user guide(ug002.pdf), all configuration has 2 times to flush pipe.
This is what I send to the cfg_in to initiate the transfer one frame,
0xaa995566; synchronization Word
0x30016001; FLR Write packet header
0x00000069; FLR write packet data
0x30008001; CMD write packet header
0x00000007; CMD write packet data(RcRc)
0x30008001; CMD write packet header
0x00000004; CMD write packet data(RCFG)
0x30002001; FAR write packet header frameaddr from .ll file; FAR write packet data (frame address)
0x280060d4; FDRO write packet head (type 1), d4(hex) = 212(dec)
0x00000000; Flush the command pipe.
then, Load the CFG_OUT instruction into the JTAG IR, then go to the SDR.
is that right?
Thank you for reading. Any information about it is welcome. Thanks in advance.