Re: 5 volt tolerant Xilinx parts

Nearly. They ARE getting out of SPLD, and older process CPLD devices.

-jg

Rick,

My point exactly. If you simulate a TTL driver, you will note it can't pull up enough to violate our spec, and so no resistor is required.

Of course, it has to be a TTL driver, and not a CMOS driver!

Now given anyone can build a pcb and sell it, I would go with the TI, or Quickswitch NMOS pass-gate voltage limiter part to be safe (and 100% compatible).

Aust> Aust> >

outlined

Anything is possible,

But you can't use 90nm for 5V. The minimum size you can use is .35u.

A combo 90 nm/ .35u process is not in the roadmap, so that makes life a bit tough.

But then again, where is the $?

Peter and I are engineers, not marketeers, so we defer to the marketing folks who seem to know just how large (small) the 5V market is....

Aust> Peter, Austin,

At what process size does the 3.3 volt compatibility go away?

I have never understood why the voltage is a problem. I understand that the thin oxide for the gate will not take the voltage. But I don't see why the IO transistors can't be made with thicker oxides. All chips have thick oxides all over the chip on many layers for isolation. Seems pretty simple to add one more oxide layer for the IO transistor gates.

I understand that this will slow the chip IO a bit and may add a bit of cost, but it is no technical hurdle and 5 volt is still a market. To be able to address the 5 volt sockets in addition to the regular market seems to be a win-win.

Austin Lesea wrote: ...

: If you havce 90nm/.35u (no reason why it can't be done), you lose all your : speed and area by having to drive the huge .35u transistors (makes for a : more expensive die).

Austin,

just for interest, is there any document showing the schematics of such a mixed voltage output stage? I think driving the PMOS of the output stage is quite tricky, without sacrificing to much current.

Bye

Are you saying that you lose all of the speed and area over the whole die or just for the IO section? If it's just the IO that would be OK in a part like this. A part aimed at the 5V interface market doesn't need fast IOs because the clock rates in that world are low. It does need the logic and RAM density of a modern part, if it wasn't any denser than an old .18u part then you might as well stick with the older part or live with external level shifting transceivers.

Uwe,

Circuits to do this are considered proprietary.

I could do a search on google for level shifters, but you can, too.

Aust> Aust> ...

This is left as an exercise for those who already know how to design these circuits,

If you don't, then it is not my place to instruct.

Aust> >

Austin Lesea wrote: : Uwe,

: Circuits to do this are considered proprietary.

: I could do a search on google for level shifters, but you can, too.

The basic concept is clear for me. An Open Collector/OpenDrain as switch and a pullup resistor ( in the discret case) or a depletion NMOS( in the integrated case) as load. But to get that at speed at low current ...

Bye

Acutally Lattice does have parts larger that the XCR3512XL. If you are looking for 256 fpBGA you can get up 768 macrocells in that package using their ispXPLD family. Not only that but each logic block can alternately be made into a large memory element so you will have plenty of room to spare.