Almost any kind of comparators? Take a look at the Platform Cable USB Product Specification
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pages 11-12 for an idea what Xilinx does to get the voltage compliance and well-defined threshold values. If you substitute the 5V LPT buffers for the CPLD, you can pretty much cut & paste your way from a Parallel-III to a Parallel-IV style cable (though you'd still refer to it in SW as a Paralell-III).
I should reiterate that having your VCC act as both a VREF and source for a DC-DC converter is a solid way to design for the 5V LPT interface and the lower-voltage JTAG interface.