Any problems with using X5R/X7R caps as buck converter output capacitors?

They work well, IME, if you can get the capacitance and voltage rating you need without breaking the bank. I've used them for a a converter supplying a couple of watts.

Best regards, Spehro Pefhany

I do this all the time. For example as output caps and as SEPIC caps. However, you have to make sure that they can stand the ripple current. Ask the manufacturer for soemthing in writing if not stated in the data sheet. For larger switchers it is usually best to place several in parallel. I rarely go above 10uF ceramic per cap.

I used to have one here where I ran a test and (knowingly) exposed it to insane currents. It could have hung on another 15 seconds but didn't. After the bang I took the broom and found it on the shovel: It's body had turned into green bubbly glass.

One thing to watch out for is the the ESR being too *low*. Some SMPS chips are unstable without enough ESR on the output!

The chip ceramics I have tried appeared to have very low ESR - in the region of 10mOhm or less.

But yes, I have used them successfully and much prefer them to electrolytics now, where it is possible to use them. (I test stability by connecting a 50 ohm output function generator to the input / output, and sweeping DC - few hundred kHz. This seems to highlight any problems). Also check switch-on transient behaviour and current limit recovery.

(sorry,

regular

ESR

would

Thou shalt not use those. And no LDOs ;-)

But they do have a current limit.

That is an interesting trick. I've done it to the input but not to the output. Thanks!

very nice trick!

X5R/X7R caps can also sing - I have seen (and heard) this dynamically varying loads. I built 50,000 50W bucks with X7R output caps - again, 10uF.

bigger caps tend to be more prone to mechanical damage & resonance (Marcon wrote a nice paper on this). And (esp. HV caps) are VERY susceptible to heat damage - soldering irons cause microcracks, which propagate into the cap & boom. green glassy goo all right!

Joerg, when not spec'd what sort of numbers do you use for ripple current?

Cheers Terry

I like to keep them well under 100mW (I^2 times ESR) and I never use tantalums in designs except maybe for the odd filter or integrator application. This paper explains it in more detail:

If a manufacturer isn't forthcoming with ESR/current data I move on and exclude them from the ECO. Mainstream companies such as AVX are usually pretty good with respect to support.

Thanks to everyone for the advice; I've ordered some 10uF and 22uF 0805 and

I have a demo board that I've been evaluating, and it has this rather odd behavior wherein the switch duty cycle is not always constant at a given input voltage. (Input is ~3-4.2V, output is 1.2V @ no more than a a couple hundred mA, buck topology, current mode regulator, so switch duty cycle always

It's usually a loop stability or layout issue. Can you post a schematic? Some chips are a bit fussy about their supply voltage which usually is derived from the input. So if the input is noisy they can act up. Sometimes it helps to supply them via a small resistor and 1uF to GND right at the supply pin. Unless, of course, it's one of those fully integrated deals where you have no choice.

current sense inputs are buggers for doing this; low Vsense controllers just make things worse - I often tack a schottky across Rsense while I get things to go. and the simple act of attaching scope probes can cause problems too. I have a jar of HCPL0302 g/d optos, with wicked dV/dt ratings. I often use these to monitor gate drive waveforms, keeping my scope the hell away from things. Hell, on one product I added the opto and associated bits to the PCB (there was a lot of room)

Cheers Terry

Oh yes, Isense. There should normally be a cap of a 1000pF or so, preferably right at the Isense pin of the chip. Even if the datasheet says that the first hundred nsec or so get blanked out really mean spikes can still pollute the innards of the chip.

yep. all fun & games. And, to add insult to injury, the problem is often WORSE at low power levels - high sense resistor voltages, and often high transformer capacitance (many turns), so Rs*CdV/dt can be ludicrously large.

Cheers Terry

Now I am not sure what you mean, maybe we are talking about different things. I meant Isense to cut the cycle when the inductor current reaches a certain level. At really low power levels a proper switcher is to behave like a Harley-Davidson at idle. One of the guys on the German NG has the problem that his LM3478 isn't doing that but pumping instead, causing half a volt of triangles on the output voltage. Up to 40msec cycles, bizarre. Kind of hard to help him with that when his workbench is 6000 miles away.

(sorry,

regular

ESR

would

A number of linear regs and some of the Simple Switchers are unstable with very low esr. Some datasheets say so, and some you have to inferr from app notes. We use one Micrel buck switcher that's very pickey about esr, and the only way to find out is by researching the output cap that's used on the eval board.

Of course, all our boards have scads of 0.33 uF ceramic bypass caps scattered around. They may not be on the power supply sheet of the schematic, but they're sure present electrically. Seems like an electrolytic with some modest esr (even a polymer) damps the ceramics enough to keep most things happy: pole, zero, pole.

Seems like roughly half the average board is power supplies these days.

We bang the output with a load step square wave, and observe transient recovery. That gives about the same info. If it rings much, it's not stable.

John

Hi Joerg,

almost all of my SMPS are Peak Current-Mode Controlled - that being said, the ones I am doing now are voltage-mode controlled, but with peak current limits.

we are talking about the same thing, but I shall elucidate.

at FET turn-on, the gate current flows the current sense resistor Rs, causing a spike. for low-power converters that switch quickly, this spike can be large - possibly even troublesome. I often re-route the gatedrive current away from Rs to avoid this.

and also when the FET turns on, it has to charge the xfmr/snubber/etc capacitance. this Cx*dV/dt current also flows thru Rs, again causing problems. not many cute tricks to get rid of this - but in DCM can turn on nice and slow (ware start-up though, it wont be DCM). of course the FET Cds doesnt cause trouble, other than heating up the FET.

making a very efficient low power PCMC supply that runs from high voltage can thus be a real PITA - low power = large Rs; high efficiency generally means fast FET switching hence high CdV/dt current into Rs :(

Cheers Terry

Terry Given wrote: (snip)

Have you tried adding a low value resistor in the positive supply line of the gate driver and capacitively coupling that to the fet source? This can form a high frequency short for the gate capacitance charging current.

It won't help with the transformer capacitive current passing through the drain, though.

Hi John,

yep I do that all the time - whenever I have to add a turn-on buffer. turn-off is easy - I use a PNP, E to gate, C to Source, B to SMPS chip, with Rg_on across the b_e junction (not that turn-off gate spikes really causes many problems).

ISTR SGS patented the current redirection scheme we are talking about, in the mid 90's. But I'm pretty sure I have a schematic in an apps note that well predates their patent, so I just do it anyway.

and yeah, the xfmr capacitance is a right bugger. which is why one must pay attention to the design of the xfmr.....

Cheers Terry

Especially bad are the cheap "hysteretic" converters - ironic since one of their selling points is "no control loop compensation required".

e.g.

Is that what happens? It does seem silly to carefully research a SMPS "output capacitor" with defined minimum ESR - only to then connect it to a circuit with a dozen paralleled super-low impedance chip ceramics!

I do that too - a swept sine wave to get a plot of effective "output impedance" vs frequency, then a fairly low frequency square wave to look at transient recovery in the time domain.

Nope. That does make perfect sense because it allows you to taylor your ESR vs frequency curve and have some where it matters for stability and 'none' where it matters for low HF ripple and low loss.

For a perfect (no esr) ceramics with a // electrolytic the overall Esr is:

Esr (C2/C1)^2 / [(1+C2/C1)^2 + (tau w)^2]

with Esr and C2 being for the electrolytic, C1 for the ceramic and tau = Esr C2.

So the equivalent ESR decrease from Esr (C2/(C1+C2))^2 at low frequency, with a 12dB/oct rate above a corner frequency given by Esr and C1//C2

That's a simple to use and very useful trick and SMPSs have a switching frequency to loop unity gain frequency ratio high enough to benefit from this.

They are equivalent, except that the transient step test easily allows some power and might shed some light on some non linear behavior.

Cool, thanks.

(I know from experience that it *does* work, but had not seen it laid out like that before).