1. Home
  2. Field-Programmable Gate Arrays
  3. NIOS SDRAM controller simulation

NIOS SDRAM controller simulation

I'm trying to simulate a NIOS based system with a altera_avalon_new_sdram_controller which is shared with the systembus.

When I try to do a write (ST) to the SDRAM I see that the cpu.the_sdram_s1.sdram_s1_chipselect is asserted. However the NIOS top level cpu.zs_cs_n_to_the_sdram_sdram_chip is not.

If I replace the SDRAM target address of the ST instruction with a different different target address I observe that the chip select signal for that device is asserted as well as the systembus write enable signal. But I can't get this to work for the SDRAM.

Any ideas?

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Reply to
Petter Gustad
Loading thread data ...

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.