I've added Virtex4 support to HDLmaker. The new version, 7.2.5, is on the web at
formatting link
HDLmaker is a free hierarchical Verilog generator licensed under a BSD style license. It generates hierarchical Verilog, simulation and synthesis scripts, pad rings, hyperlinked HTML versions of the Verilog code, schematics, and PADS PCB netlists. It also has a C like language which allows you do complex code generation. It primarily aimed at FPGA and ASIC design but can also be used for PC board design. The VHDL support has been deprecated.