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Memory width on Spartan-3 boards

Hi Simon,

I've been investigating lately *exactly* the same issues you have, however I finally made a decision and ordered the NuHorizon's board.

While the width of the SDRAM was a deterrent, simply placing two read cycles back-to-back should solve the obvious problem.

For curiousity's sake, are you working on a commericial or academic project?, I am also working on implementing a MIPS based system-on-a-chip. If you pick up that particular board, maybe we could help each other out, since the kit includes next to no documentation.

Please contact me by e-mail if you are interested.

Thanks,

Edm> So, I have a 32-bit processor design which I'd like to move to the

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Edmond Cote
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Yes, but I have *plans* [grin] The idea is to use the burst-mode of the DDR2 SDRAM to fill a line of i/d cache at once, taking a hit on fetching the first entry in the line, but hopefully winning overall. For that to work though, I want the access to RAM to be as fast as possible. It would of course work with 2x16-bit access, but I want speed :-)

I've more or less decided to go for the BroadDown2 board - I think the possibilities for adding stuff onto it are better, and I want SDI in and analog-video --> video decoder chip (Phillips SAA7115 probably). I want to put an MPEG2 decoder / encoder (one at a time) onto the FPGA as well as the CPU core for general purpose stuff. It's going to need an SDRAM controller, and probably a PCI interface too... Like I said, plans :-)

So, I'm looking really at the 1.5M part rather than the 400k part, which means lots of expense (Foundation, aaarrggghhh), and I'm going to try and get as much done *before* I cough up the cash to decide if I can actually *do* it or not...

As for motive, well at the moment it's purely curiosity on my part, but if it all pans out well, there is a commercial possibility (I work in the professional post-production industry, and there is a gap I could fill...)

Simon.

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Simon

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