Hi Folks,
The process below uses two enable signals ANDed together.
some_proc: process (CLK)
begin
if (CLK'event and CLK='1') then
if (CLKEN = '1') and (XYZ = '1') then
-- signal assignment
end if;
end if;
end process;
After synthesis and place and route (targetting XC2V3000-FG676-5) of a VHDL design that uses this structure in several processes, the critical path involves the CLKEN signal with the main delay being a net fanout of CLKEN of
52 taking 5.4 ns.
So, the question(s)
(Q1) Is this style ok or should avoid ANDing enables just like I would avoid ANDing a clock?
(Q2) I think that the delay and fanout of CLKEN would be high anyway even if it was not being ANDed with XYZ - agree? (the critical path includes a tilo which I assume is the AND taking place but this tilo is only 0.382 ns)
Many thanks for your time,
Ken