Not at all. Programmers juggle instruction/statement flow all the time to reach timing closure in C and asm for device drivers and embedded applications in many fields .... such as software driven stepper motor controls. Such low level programmers also have training in understanding bit level device interfaces, and related timing. They frequently do not have board level hardware training or experience, to deal with power, board level signal integrity, and related issues.
The reason for C based HDL/HLL's is to expand the field to include related sytems and embedded programming talent to be able to effectively, and comfortably, write "programs" for HDL/HLL FPGA based designs which effectively instantiate the same hardware that VHDL/Verilog would with similar syntax statements. We do this by preserving sequential semantics with parallel statement execution of standards based C. Also removing fine grained access to creating multiple fine grained clocking sematics that are standard for pure HLLs. For those that are doing device level or machine level interfaces, writing C FSMs to netlists is substantially the same as coding asm or C for similar low level hardware interfaces. Remarkably the same task and skill set as writing drivers or embedded hardware controls.
Programs are FSM's and data paths.