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- 07-04-2003
posted on July 4, 2003, 3:51 am
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Hi everyone, <BR>
Iam an student having doubt in LVDS
communication, <BR>
Let say xilinx vertex FPGA is used for this pupose. <BR>
I have LVDS transmitter and receiver,
No AC coupling is been used between them. <p> Let say transmitter is in
one board and receiver is in another board connected through backplane (no AC
coupling), <p> I am not recoevring the clock at the receiver, clock
(77.77MHz) given to both transmitter and receiver through single source. <BR>
Do i need to use any scrambling or
encoding techniques before transmitting the bit stream over LVDS to remove DC
offset for better BER? <p>Thanks in Advance,
Iam an student having doubt in LVDS
communication, <BR>
Let say xilinx vertex FPGA is used for this pupose. <BR>
I have LVDS transmitter and receiver,
No AC coupling is been used between them. <p> Let say transmitter is in
one board and receiver is in another board connected through backplane (no AC
coupling), <p> I am not recoevring the clock at the receiver, clock
(77.77MHz) given to both transmitter and receiver through single source. <BR>
Do i need to use any scrambling or
encoding techniques before transmitting the bit stream over LVDS to remove DC
offset for better BER? <p>Thanks in Advance,
Re: information required
Dear Sir, <p>Thanks, is it ok if i designed with DC coupling for 155.54 MHz
serial LVDS link or do i need to use AC coupling. <BR>
I have used Xilinx termination technique (resistor network) at both transmitter
(Spartan FPGA used) and receiver (spartan FPGA used). <p>Is the design will
work for above configuration, <p>Thanks in Advance, <p>Regards, <BR>
Karthik
serial LVDS link or do i need to use AC coupling. <BR>
I have used Xilinx termination technique (resistor network) at both transmitter
(Spartan FPGA used) and receiver (spartan FPGA used). <p>Is the design will
work for above configuration, <p>Thanks in Advance, <p>Regards, <BR>
Karthik
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