Hi everyone, Iam an student having doubt in LVDS communication, Let say xilinx vertex FPGA is used for this pupose. I have LVDS transmitter and receiver, No AC coupling is been used between them. Let say transmitter is in one board and receiver is in another board connected through backplane (no AC coupling), I am not recoevring the clock at the receiver, clock (77.77MHz) given to both transmitter and receiver through single source. Do i need to use any scrambling or encoding techniques before transmitting the bit stream over LVDS to remove DC offset for better BER? Thanks in Advance,
- posted
20 years ago