Hi all,
Does anyone know the right steps to make ISE infer DDR registers from a RTL code? I am following the template that ISE suggests in their answer record #15776. Apart from this, I also make sure to set the IOB option during MAP. I still cannot see the dual-data rate flops being used in the map report.
However, when I open FPGA editor, I can see that my two flops were mapped to registers that are placed in the same IOB. How do I know for a fact that the IFDDRSE (or a corresponding) primitive is actually being used?
Thanks
Anil