Hi:
I have a Verilog design for a Xilinx XPLA3 CPLD consisting of a toplevel module that instantiates several other modules. I am developing in WebPACK 5.2i.
The current design requires a single clock signal. I am supplying that clock through one of the INn/CLKn inputs of the XPLA3 architecture.
Must I do anything special in the Verilog in order to ensure that the clock is routed through the chip using the dedicated clock distribution lines rather than through general purpose logic signal routing?
For instance, should I use BUF, BUFG, and/or BUFSR ?
Thanks for comments. Exerpts of my code shown below:
From myproj.ucf file:
NET "Clk10kHz" LOC = "p89";