For those of you interested in research on the development of FPGA CAD and architecture, I am pleased to announce the release of new version of VPR, Version 5.0 Beta. This is a CAD tool suite targeting hypothetical FPGA architectures that enables both FPGA architecture and CAD exploration research. Its primary functionality is to provide packing (clustering), placement, routing and timing analysis for FPGA architectures described by an architecture description file.
Building on the widely-used VPR 4.30, VPR 5.0 adds three important new features:
- Single-Driver Routing Architecture (also known as Direct-Drive or Unidirectional routing architectures) now commonly used in major commercial FPGAs.
- Heterogeneous logic blocks - the ability to describe different hard blocks, in addition to the regular soft logic. A new form of architecture description file permits this.
- A wide range of transistor-optimized design files, spanning architecture, different area-delay tradeoffs, and IC processes down to 22nm, based on the Arizona PTM process models. For each logical architecture, we provide different electrical designs modeling the different IC processes *and* different transistor-sizing goals with respect to the importance of area and delay.
In addition, in an attempt to maintain VPR's legendary software quality, we include regression tests that allow the developer the ability to test changes for correctness and quality.
Also, we are providing an open source front-end CAD flow from Verilog to the T-Vpack input step. It begins with ODIN (for Verilog parsing and elaboration), passes through a modified version of Berkeley's ABC logic synthesis (thanks to Alan Mishchenko for support of ABC) that permits heterogenous structures to pass through, unhurt.
Download Location:
The license for T-VPACK and VPR is the same as that granted previously: non-commercial, not-for-profit use (see the download page for details). The license of the front-end ODIN CAD flow is open source.
As this is a Beta release, we are interested to receive feedback and bug reports. Please send those to snipped-for-privacy@eecg.utoronto.ca. We intend to produce a non-Beta release in the near future, incorporating feedback and problem reports. We also hope to engage in longer-range improvements to this software and are interested in suggestions on that front.
CREDITS: In addition to the people listed above, this new release is the result of many people's work, including the original author, Vaughn Betz, who set a very high standard of quality that is hard to meet. Sandy Marquardt wrote the original timing-driving packing and placement. Andy Ye created the first version of the single-driver routing, which Mark Fang improved. Danny Paladino's research influenced the architecture description work incorporated here. Russ Tessier helped begin this project when he was visiting Toronto, and Mark Fang and Andrew Ling contributed to that early work. Ted Campbell was instrumental in the new heterogeneous block and routing architecture work. Ian Kuon's research and efforts contributed the new architecture files describing a wide range of architectures, in different processes and optimized for different target area and performance. Jason Luu and Peter Jamieson were key developers instrumental in the development and release of this version of the software.
Jonathan Rose
-------------------------------------- Jonathan Rose, Professor and Chair The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto
10 King's College Rd, Toronto, Ontario CANADA M5S 3G4--------------------------------------