FPGA dev kit with 4-8 Cyclones or Spartans

Why?

What is it you are trying to show, prove, or do?

It would be nice to know.

Austin

Pico Computing

has done some interesting work with multi-FPGA kits. At a Xilinx X-Tech event, they had a PCIe board with 15 S35000s. I have never done business with them and can't make any other comments about their quality.

- Nathan

Um, what would be wrong with 4 Spartan starter kits and some duct tape?

G.

It is most cost-optimal for crypto-tasks, if I'm correct, of course. Like it was done there:

Ah, ok then, 120 Spartan starter kits and a bigger roll of duct tape :)

For something so massively parallel and where each FPGA presumably spends almost all of its time operating independently, I would think some cheap off-the-shelf single-FPGA module in quantity might actually be the easiest way to go. Probably not a problem to hook up 120 USB devices to a PC to control them or whatever. Might get a little warm though.

G.

Not quite a single board solution but we can offer a stacked array of boards over a number of our products that fit together nicely. Have a look here

This is a build to order option and can be done easily on our Broaddown2, Raggedstone1, Drigmorn1, Broaddown4 boards. It may also be possibly to stack our Darnaw1 module (PGA) but we have never bought the socket for this as yet so that would need to be confirmed.

Also worth considering is our Hollybush1 product -

Again a stacking approach but this time the standard PCI104 connectior can be used in a dedicated(non standard) fashion to interconnect the stack. All the pins on this interface can be any direction as defined by FPGA build and used as you like. Our OVERCOAT technique can also be used on this board to add 116 I/O on top of the PCI104 interface if more interconnect is needed. All that would be needed would be a power card to power the array and we are working on that and I think there are some products out there already for that.

John Adair Enterpo> Hello.

Just a couple more thoughts on this (I'm not a crypto person but hey, this is Usenet):

I'm not sure how interesting having such a device (as described at that URL) would actually be. They talk about being able to crack symmetric cyphers with "roughly" 64-bit keys. Well for standard DES "roughly" is only 56 bits as I recall, so when they say the average time to break a DES key was 6.4 days, that means a real

64-bit cypher would take an average of 4.5 years with a worst case of 9 years at the same speed.

Cracking plain DES is a clever demonstration of parallel computing, but these days just isn't all that interesting any more I think.

The 120 FPGA device described is unlikely to be good for anything other than brute-force parallel tasks, and in the crypto world I don't know that there are many other interesting things you can do that are of similar complexity to cruddy old single DES.

It seems to me (again not being a crypto guy) that all these cracking machines may be somewhat uninteresting for many real-world applications because they must be known-plaintext attacks as they rely not only on being able to do fast decrypt operations to test each possible key, but also being able to determine whether the key was correct or not in a similarly short period of time.

This might not be so easy to do depending on how much knowlege you have about the plain text of the message you're trying to decrypt.

Anyhow, I can't really think of anything interesting to do with a device such as the one you're asking about.

G.