I want to be able to use the fastest possible paths within a SpartanII FPGA to create internal signals which are simple copies of each other linked in a chain. Delay between each should be in the order of a few tens to hundreds of picoseconds. All of the created signals should however be usable by other internal logic (in fact on D inputs of a chain of flip-flops clocked all the same) My first idea was to define a chain of BUF "components", and see what happens. As feared, the (Foundation) development tool just merged all the signals (No BUF generated). Forcing a KEEP attribute on all the signals just did not help. I tried with LUT1's. This works but is much too slow for the application. Looking at the FPGA Editor gave me the idea of using the MUXCY, MUXCY_L or MUXCY_D components of the SpartanII library. Some sort of a miracle happened then: the dedicated carry chain was selected, running thru the expected number of CLB's, and speed was excellent. But to my great surprise, only one flip-flop out of two hooked onto the outputs of the MUXCY components was selected as being part of the same cell. The second FF was placed in a totally different CLB. This is not exactly what I expected, since the application requires a very close matching of delays. Any idea why this happens ? Possible corrections ? Thank you beforehand.
- posted
19 years ago