Hello,
I have added a TFT controller peripheral to an already working Microblaze system with minimal implemented functionality. Now, I cannot access the data bus. Please see the error print out by XMD below.
The new peripheral is connected via DCR bus for register access (slave DCR). There is a PLB2DCR bridge. It is also connected to PLB bus via its master PLB ports.
Do you have any suggestions on what might be wrong? See below for system details.
------------------------------------------------------------------------------------- XMD% targets
------------------------------------------------ System(0) - Hardware System on FPGA(Device 3) Targets:
------------------------------------------------ Target(0) - MicroBlaze(1) Debug Target*
XMD% dow mb0_default/executable.elf System Reset .... DONE Downloading Program -- mb0_default/executable.elf section, .vectors.reset: 0x00000000-0x00000003 section, .vectors.sw_exception: 0x00000008-0x0000000b section, .vectors.interrupt: 0x00000010-0x00000013 section, .vectors.hw_exception: 0x00000020-0x00000023 section, .text: 0x00000050-0x0000ac6f section, .init: 0x0000ac70-0x0000ac97 section, .fini: 0x0000ac98-0x0000acb7 section, .ctors: 0x0000acb8-0x0000acbf section, .dtors: 0x0000acc0-0x0000acc7 section, .rodata: 0x0000acc8-0x0000b385 section, .data: 0x0000b388-0x0000b97b section, .eh_frame: 0x0000b97c-0x0000b97f section, .jcr: 0x0000b980-0x0000b983 section, .bss: 0x0000b988-0x000105c3 section, .stack: 0x000105c4-0x000109c7 ERROR: Failed to download ELF file
D-Side Memory Access Check Failed Section, 0x0000b988-0x000105c3 Not Accessible from Processor D- Side Interface
XMD%
------------------------------------------------------------------------------------- The stack size is 0x400, heap is 0x0.
- I assume it is ok for this peripheral to be connected as master to PLB for external memory access.
- I tried changing C_DCR_BASEADDR to something other than zero just in case. But I assume that DCR address does not interfere with PLB bus itself and should be relative to PLB2DCR's base address? PARAMETER C_DCR_BASEADDR = 0b0010000000 PARAMETER C_DCR_HIGHADDR = 0b0010000011
- PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0x10000000 coincides with the beginning of RAM. I can see a pattern of RGB dots across the whole screen after the bitstream's upload.
- I did not connect the controller's TFT_DPS out port (scan direction). Also, FPGA's VGA_COMP_SYNCH pin is not connected either as I am not sure where to and their descriptions do not really match.
------------------------------------------------------------------------------------- MHS snippet:
------------------------------------------------------------------------------------- BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000ffff BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_port END
BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000ffff BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_port END
BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = ilmb_port BUS_INTERFACE PORTB = dlmb_port END
BEGIN mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 1.00.c PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0x84400000 PARAMETER C_HIGHADDR = 0x8440ffff BUS_INTERFACE SPLB = mb_plb BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg PORT Debug_SYS_Rst = Debug_SYS_Rst END
DDR is at 0x1000000, 128Mb
BEGIN xps_tft PARAMETER INSTANCE = xps_tft_0 PARAMETER HW_VER = 1.00.a PARAMETER C_DCR_SPLB_SLAVE_IF = 0 PARAMETER C_TFT_INTERFACE = 0 PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0x10000000 PARAMETER C_DCR_BASEADDR = 0b0010000000 PARAMETER C_DCR_HIGHADDR = 0b0010000011 BUS_INTERFACE MPLB = mb_plb BUS_INTERFACE SDCR = dcr_v29_0 PORT TFT_VSYNC = VGA_VSYNCH PORT TFT_HSYNC = VGA_HSYNCH PORT TFT_VGA_CLK = VGA_OUT_PIXEL_CLOCK PORT SYS_TFT_Clk = tft_clk PORT TFT_DE = VGA_OUT_BLANK_Z PORT DCR_Rst = sys_bus_reset PORT DCR_Clk = sys_clk_s PORT TFT_VGA_R = VGA_OUT_RED PORT TFT_VGA_G = VGA_OUT_GREEN PORT TFT_VGA_B = VGA_OUT_BLUE END