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Interrupts and Analog Devices ADuC842

Hi,

We are experiencing some issues with external interrupts resetting an Analog Devices ADuC842 controller (8051 family). The system we are working on analyses sensorial data from a rotary encoder connected to EX0. The interrupt is configured to be level-triggering. In our current set-up, the controller spontaneously resets when the rate with which the sensor interrupts occur exceeds certain level. We know from counting the number of CPU instructions in our ISR and estimating the number of interrupts, that the problem is likely to stem from the controller not being able to process the interrupts quick enough. What we fail to understand, though, is why this would reset the controller as we would expect the interrupt system to either queue interrupts occurring too soon to be processed, or to ignore them altogether.

Can someone help us understand what is / might be going on?

To set up the interrupt we've got the following code:

IT0 = 0; /* Configure interrupt to be level triggering. */ EX0 = 1; /* Enable external interrupt 0. */ EA = 1; /* Global interrupt enable. */

Our ISR:

static void encoder_isr(void) interrupt 0 { unsigned int new_AB; unsigned int old_and_new;

/* Get the new A and B values by masking the entire port byte to avoid interference from pending interrupts: */ new_AB = (P1 & 0x18) >> 3;

/* Combine the old and new A and B values. The resulting bit pattern indicates the direction of movement. eg: old = 0000 0011 ---------

Reply to
Walter Smits
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First you should use the "using" statement so you do not have to push everything on to the stack (like encoder_isr(void) interrupt 0 using 1) you could be over flowing the stack. You could be spending so much time in the interrupt that your watchdog resets. the 8051 does not queue interrupts. But since you are level sensing you could go right back to the int on the next instruction.

Reply to
Neil Kurzman

Thanks for your reply. We solved the problem after we got in touch with Analog's tech support: the ADuC842 has a bug that resets the instruction pointer to 0 if a level-triggering interrupt is cleared too early (within 9 core clock cycles). In case someone else runs into the same kind of problem: see anomaly er10,

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Fortunately for us we could easily adopt our design to be edge triggering.

Walter

Reply to
Walter Smits

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