1250gbps input on virtex-5

Kolja,

I suggest you work with your FAE.

It is challenging (for the signal integrity alone, not even considering the FPGA).

The V5 has serdes capability built in per pin (pair), so this is what gets used (the fabric doesn't have to run this fast -- it can not).

LXT, SXT, FXT all have identical LVDS. Speed grade does no apply to LVDS (they are all graded the same). How the design is done will determine what speed grade is required.

I suspect you meant "how many hoops do I have to jump through" (not loops).

I do not have an answer for you, other than people are doing this sort of thing.

Aust> Hi,

Kolja, there is a very good app note (43 pages long) that describes the design, and its dynamic alignment in gory detail. This is all based on actual testing of Virtex-5 chips on our evaluation board. Greg Burton, the applications engineer, drove the design all the way to 1.4 GHz, where the eye got very small.(see page

25). Good luck with your design, you are in good hands with this app note, XAPP855

Peter Alfke

Thx. That is exactly what I was looking for. (Actually I need XAPP860) As I read this we have multiple options:

- use a -3 speedgrade

- use a power supply 5% over nominal voltage with extremely good regulation

- rely on the fact that the signal quality will be better than what is used in the application note.

We probably will choose all three options at once. :-) Are -3 devices available? Our distributor could not give us a quote.

Kolja

Hi Kolja, Indeed, XAPP860 is a big improvement. In fact, it strikes me that with a little work, an initial Rx cal with a training pattern isn't necessary for eye alignment and the V5 can dynamically align to random data by comparing the outputs of the master and slave ISERDES. Word alignment could be achieved by looking for known patterns in the incoming signal, e.g. F628 for SONET. Cheers, Syms.

Kolja, I should have referred you to the XAPP860. My oversight... Regarding -3 devices, they do exist for all the smaller part types, but not for the largest ( '200 and above).

-2 might be good enough for your application. -3 has a faster clock distribution, but there is little (if any) difference in the LVDS and ISERDES structures. Gru=DF Peter

Easy enough. The application notes link to each other.

At those speeds 100ps make a big difference. The application notes show, that at 1200Mbps the sampling windows is twice as large on a -3 than it is on a -2 device. However, it really seems to be the case that -2 is good enough. Especially as we can run the device easily at +3% supplies.

Thank you for the pointer,

Kolja