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Hi, there:=20
I have found that Xilinx synthesis directive "mult_style =3Dlut" can = only be=20 applied to either a reg/wire directly under a module, or applied to the=20 module itself.=20
A complicated design or module may contain multipliers wrapped in=20 a task or function, in which situation I may or may not define a = wire/reg.=20 I have discovered that mult_style didn't work in either a function or a = task.=20
The use of mult_style on the module itself applies to ALL the multiplers =
in the module irregardless of whether a multiplier is wrapped in a = function/ task or not.=20
so, how do I constrain "mult_style =3Dlut" on my multiplier in a = function/task=20 statement while leave my bare multipliers to BLOCK alone?=20
Thanks.=20
Kelvin