Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice

Is there some way of comparing how big Altera devices are versus Xilinx devices. Whereas Xilinx lists the "System Gates", Altera lists logic elements. So, I am not sure how to equate the product families from the two vendors. Any help will be appreciated.

Thanks Sumit

They are both based on 4 input LUTs, if you do a little math you can figure out how many LUTs they have in a device. As a first approximation this is a pretty good measure. Comparing the RAM is little easier since they both specify the number of bits of Block RAM although you have to take into account that Xilinx LUTs can also be used as RAM whereas Altera uses dedicated small Block RAMs instead of LUT RAMs.

Ah, yes I did!! :)

Rick,

Nice post. One thing I'd like to point out though:

You should check out the Stratix II ALM. It has very powerful arithmetic -- you can use a 4-LUT in front of each input of the adder when you are adding two numbers. That is more powerful than either Stratix or Virtex2. Also, it can add 3 numbers at a time, which reduces the depth and size of adder trees (this feature is also unique to Stratix II.

Vaughn

Very interesting marketing BS. Have you realy read the original questions and try to answer those?

Sumit, if you need DSP functions, look at FPGA's with DSP alike architectures, if price is important (obviously, you are looking for high volumes), try to figure out what will be to total system cost (don't forget the configuration device!). If you want to design a uC in your FPGA, add security, etc... in other words, make a checklist with mins and max's and try to describe your design to the FAEs of Actel, Altera, Lattice and Xilinx (if you want to compare them all). If you like the idea of flash based - some devices will fall of the checklist, if you like SRAM, some others will fall of, etc. If you need 5V tolerance, well ... you won't select one of the newer devices as the aren't tolerant at all.

Best regards,

Luc

Vaughn, Peter, Others

How much faster are the 90nm parts over the 130nm parts? I saw someone on this forum say that you can achieve almost 2x performance. Is this because of the move from 130 to 90 or is it because of the new architectures of Stratix-II and Spartan-3 etc ? Is the new architecture a product of the fact that you can fit more logic at 90nm than was possible at 130nm ?

Thanks Sumit

Paul

Are your 90nm parts 2x better performance because of going to 90nm process or because of the new/better architecture ?

Thanks Sumit

Hi Sumit,

Stratix II (90 nm) offers a 50% average performance improvement over Stratix (130 nm). In addition, some critical blocks (DSPs, memories, I/Os) were sped up significantly. This is a combination of architecture, process technology, and elbow grease in the electrical design. The main architectural enhancement is the Adaptive Logic Module (ALM) which replaces the Logic Element of Stratix. There are some additional tweaks, but I frankly can't recall which ones are user visible. And good electrical design can always help -- since some features from Stratix II were an evolution from Stratix, designers could spend more time tweaking the design rather than concentrating strictly on functional correctness.

As far as process goes, it used to be that moving from one process to a smaller one would give automatic speed ups and a smaller die size to boot. The trade-offs are more complex these days. The die size savings are still there, but the speed-up is not automatic. In smaller processes, we thin the gate oxide to improve transistor speed (~linear with gate oxide thickness). But we must then shrink the core voltage (Vcc) to reduce Vgs otherwise the oxide breaks down (reliability issue); the thinner oxide also causes increased gate leakage, which is mitigated some by reduced Vgs. Reducing Vcc also reduces dynamic power (quadratically). As we scale down Vcc we need to scale down the threshold voltage (Vt) otherwise the transistor gets too slow (Ids = k(W/L)(Vgs - Vt)^2). But the lower the threshold, the less "off" the transistor is when Vgs=0V. And of course the gate length (main process feature) is shrinking, which (linearly) increases transistor speed but greatly increases sub-threshold leakage. So we have to pick-and-chose when to apply fast but leaky transistors and when to stick with low-power but slow transistors (with longer gate lengths, higher threshold voltages, thicker gate oxides, etc.). There are many other tricks that can be employed on the speed/power front, some of which cost area or increase manufacturing costs, and all make our job designing the FPGA that much more fun :-)

One other process change was the move to low-k inter-metal dielectric. This reduces the capacitance of metal routes, in exchange for some additional manufacturing & materials challenges. Low-K took a while for the semiconductor industry to get right, but it's now mature enough that we feel we can produce low-k chips with no yield impact. We've been playing with low-k for a while but decided not to roll it out in our products until Stratix II.

The architectural changes are somewhat independent of process, though there is always some tweaking possible, for example as the ratio of logic vs. routing delays change over process. Also, as power becomes more important, many architectural choices will need to be revisted to find the right speed/area/power/complexity trade-off. For example, the ALM offers better power than the equivalent circuit in LEs since more logic is captured into locally (vs. programmably) routed circuitry; this is more important at 90 nm where power is becoming a bigger factor. So while there is some connection to process, most architectural improvements are just the result of us having had another two years to think!

Regards,

Paul Leventis Altera Corp.