Chaos in FF metastability

Let's go back to the word origin and the definition: meta (from the Greek) means "between", stable (from Latin) means, well, stable...

Reply to
Peter Alfke
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Sure, I agree; I thought I'd covered that with my comment on the switching energy and the damping.

Having said that, I like to think of metastability in terms of hazards in K-maps. If you do the wrong thing to the inputs, and the K-map says that the output oscillates (or you have one switching input and a hazard), then you've got metastability. What actually happens in a practical circuit will depend on how it's constructed.

Evan

Reply to
Evan Lavelle

But you have not responded as to why the FF can not oscillate. The FF is more than just a penl standing on end or a ball on a hill. A FF is a dynamic system with feedback and delays. My schooling taught me that with the right combination of delay and gain (or the wrong combination) it can oscillate. What makes these FFs different?

The pen analogy is not a lot different from the pendulum. Yet a pendulum can be chaotic! I think the pen is only good as a first order approximation. For this sort of issue, the analogy requires further scrutiny.

Reply to
rickman

That's different than metastability. You are talking about dynamic hazards (race conditions). Given a sequence of inputs and a circuit with a dynamic hazard, the circuit will respond exactly the same way every time the same input (levels and timing) is applied. Although the operation may not be what the designer intended due to the dynamic hazards, it is still a deterministic system. Metastability is a very specific condition where the outcome is not deterministic. It occurs in a system with positive feedback when the input changes occur in such a way (with a very specific timing) that the circuit ends up balancing in a state that is neither '1' nor '0'.

Reply to
Ray Andraka

Let me continue the story: And that balanced state may even appear like a legitimate 1 or 0 on the circuit output, but the internal falling back into the stable 1 or 0 may (or may not) create an output transition that occurs at a non-deterministic time after the clock edge that started the operation. It is this unknown (and unknowable) delay that can create havoc in an otherwise synchronous system.

Peter Alfke, Xilinx

Reply to
Peter Alfke

Put this into a Spice pgm, and try it.

In fact, (good) spice should be able to show the settling-time-extension effects of metastability quite well. It would need carefull sweep of the drive voltage, at the instant the clock does the hand-over.

The FF I am used to, is Analog transmission gates, around single CMOS INV/OR gates - two forming the regenerative latch.

These simple 'unbuffered' CMOS structures have finite analog gain, even at their peak, in the linear region. (unlike TTL ones )

To build an oscillator, you must hold them in the linear region (DC), and provide phase shift at some other frequency, where the loop gain is still over unity.

Yes, there are parasitics all around, but the FF lacks the linear-bias mechanism, so it cannot sustain oscillation.

I am sure some would look pretty knarly, as they settled, and may not be monotonic, but these times will be very short. During this settling time, they will also be at their most sensitive to crosstalk effects.

-jg

Reply to
Jim Granville

If you have studied Op-amps, which have negative feedback instead of positive feedback, you are probably familiar with the bode plot.

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The key to stabilizing the op-amp is to insure that the feedback gain (open loop gain/closed loop gain) drops below unity before the additional phase shift reaches 180 degrees. For instance, take a look at the Open Loop Gain and Phase plots on page 7:

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In this case, the phase shift reaches 180 degrees at about 250 MHz while the gain is still 10dB. If you use this op-amp in a unity gain application, it will oscillate (hence the recommendation to use it for gains of 10 or greater).

A similar analysis applies to flip-flops. The main difference is that here the feedback is positive (-360 degrees) and so latching to one side or the other is a stable state. If you get an additional -360 degrees of phase shift before the open loop gain reaches zero, the device can oscillate at that freqency if stimulated properly.

2 gain stages with single pole RC roll-off will have a maximum additional phase shift of -180 degrees. Cascading 4 or more gain stages will usually ensure that the phase shift exceeds

-360 degrees before unity gain is reached due to the presence of higher order poles & wire delays.

Daniel Lang

Reply to
Daniel Lang

Yup. Studied, used, taught about :-)

Indeed. That's a nice simple explanation that's often missing from the textbooks.

OK, thanks for that insight - the (rather obvious) point I'd missed was that you need an extra *360deg* of phase shift to get the thing to oscillate, not 180deg.

OK. Thanks for the nice and appropriate description.

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Reply to
Jonathan Bromley

Two reasons why I can't... 1) I don't have Spice 2) I don't have "this".

I am sure it can, but several posts here claim that CMOS FFs can't oscillate and I am asking how people know this is a true fact. Obviously simulating it or hooking up a test circuit can't prove it won't oscillate. That can only prove it won't oscillate under those conditions.

Why do you call this "unbuffered"? Don't the gates create gain and delay? The more I think about this, the more I am starting to believe that a FF is capable of chotic behavior.

I don't think that is true. The TTL FFs (or coupled inverters) that oscillate don't remain in the linear region. They peg the rails and the delays cause them to peg to the other rail when the feedback takes effect.

Reply to
rickman

1) Spice is free, written at U.C. Berkeley CAD.

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There are paid versions, with fancy features, or encypted models support, or beter GUIs. If you do a lot of Spice work, one of the paid versions might be worth the cost.

I've also heard good things about this version:

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I have not tried this version. Any feedback from users?

2) This is a fairly simple netlist with 5 or so transistors: take a half a hour to enter at most.

-- Phil Hays (Xilinx, but speaking for himself)

Reply to
Phil Hays

On a sunny day (Thu, 06 Jul 2006 18:32:23 -0700) it happened Phil Hays wrote in :

This is a nice one:

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ltspice is free too. Also it has lots of linear regulators already modelled. Works in Linux wine too: wine scad3.exe And there are many examples in it.

Reply to
Jan Panteltje

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