Sinewave oscillator without gain control.

This is obviously true. Why do you think you need to tell us about it?

The accuracy of the results depends - first and foremost - on the accuracy of the Spice models. The only reason you could have to trust the LTSpice results would be that the real circuit gave the same results under the same conditions. John May has gone that far - you and I don't seem to have.

But why bother?

For the circuit - as simulated. A real circuit will behave differently - it will have stray inductances and capacitances which are not include in the schematic and the device models merely approximate the actual performance of the device being modelled - mostly accurately enough for all practical purposes, but this map really isn't the territory.

LTSpice simulations can be a reliable guide to what won't work. They are less reliable guides to ultimate performance.

You do have to add gain control to get a constant output level, and you do have to do it without introducing too much extra distortion.

Who cares. The distortion levels we are quibbling about are in the same range as the rounding error in the Spice numerical integration.

You can get 20-bit A/D converters that sample quite fast enough to monitor a 1kHz oscillator, and you can do a Fourier transform on the stored output of the A/D. It wouldn't cost me any money because my current computer has an audio input that works that way, and some software from an old friend in Scotland that lets me use it as signal monitor. It would cost me time because I installed the software perhaps ten years ago and have only used it once.

You do make me laugh sometimes Bill. Your circuit doesn't come anywhere close to 120dB but it does depend on which simulator you ask. Adding a FET gain stabilizer to the circuit I posted seems to have negligible effect on the distortion. So I'd concentrate on the oscillator distortion level rather than the gain controller contribution if I wanted to attempt better than 120dB.

In article <vmum11$n7g$ snipped-for-privacy@nnrp.usenet.blueworldhosting.com>, Edward Rawde snipped-for-privacy@invalid.invalid wrote: <SNIP>

If I read the specs on capacitors, I fear that even a passive filter would increase the distortion unless rigid air capacitors are used. Comment? In general: In how far are passive electronic components ideal, distortion free? (I read bad things about SMD capacitors.)

Groetjes Albert

COG/NPO ceramics do not have the extreme non-linearities of some of the other types. Nor are they piezoelectric. The only problem is that anything larger than about 10nF gets large, expensive and possibly unobtainable. PPS capacitors are available in larger values and have a low, but not zero voltage coefficient. John

Open LT Spice and make a 1 KHz sinewave voltage source. Run for 10 seconds and FFT. The 3rd harmonic is down 48 dB.

So Spicing low distortion oscillators might not be an exercize in reality.

"john larkin" snipped-for-privacy@gct.com wrote in message news: snipped-for-privacy@4ax.com...

The following circuit was simulated in LTSpice 2.1.0 with all possible updates as of today. I stopped the simulation after two seconds worth of watching source, input and output. I then selected a sample of about 20ms near 2s. I then did an FFT using the current zoom extent with Blackman-Harris window on each trace in turn. The following results give the difference between 1kHz and 2kHz. source -240dB input -190dB output -120dB

How far this has anything to do with reality I do not know.

Version 4.1 SHEET 1 2196 932 WIRE 0 -416 0 -448 WIRE 208 -288 48 -288 WIRE 112 -208 112 -240 WIRE 48 -192 48 -288 WIRE 80 -192 48 -192 WIRE 208 -176 208 -288 WIRE 208 -176 144 -176 WIRE 256 -176 208 -176 WIRE 320 -176 256 -176 WIRE 0 -160 0 -336 WIRE 80 -160 0 -160 WIRE -224 -144 -224 -240 WIRE 0 -112 0 -160 WIRE 0 -112 -64 -112 WIRE 112 -112 112 -144 WIRE 736 -112 672 -112 WIRE 864 -112 816 -112 WIRE 0 -80 0 -112 WIRE -64 -64 -64 -112 WIRE 752 16 752 0 WIRE -224 32 -224 -64 WIRE -64 32 -64 0 WIRE 0 32 0 0 WIRE 480 32 400 32 WIRE 560 32 480 32 WIRE 672 32 672 -112 WIRE 672 32 640 32 WIRE 720 32 672 32 WIRE 864 48 864 -112 WIRE 864 48 784 48 WIRE 896 48 864 48 WIRE 1024 48 976 48 WIRE 1184 48 1088 48 WIRE 1248 48 1184 48 WIRE 400 64 400 32 WIRE 688 64 672 64 WIRE 720 64 688 64 WIRE 752 96 752 80 WIRE 1248 112 1248 48 WIRE 400 176 400 128 WIRE 480 176 400 176 WIRE 512 176 480 176 WIRE 1248 208 1248 192 WIRE 400 240 400 176 WIRE 400 400 400 320 FLAG 752 0 V+ FLAG 1248 208 0 FLAG 1184 48 output FLAG -224 32 0 FLAG 752 96 0 FLAG -224 -240 V+ FLAG 688 64 half FLAG 112 -112 0 FLAG 112 -240 V+ FLAG 256 -176 half FLAG 0 32 0 FLAG 0 -448 V+ FLAG -64 32 0 FLAG 400 400 0 FLAG 480 32 input FLAG 480 176 source SYMBOL voltage -224 -160 R0 WINDOW 123 0 0 Left 0 WINDOW 39 10 135 Left 2 WINDOW 0 10 0 Left 2 WINDOW 3 15 104 Left 2 SYMATTR InstName V2 SYMATTR Value 32 SYMBOL res 992 32 R90 WINDOW 0 -4 57 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 600 SYMBOL res 1264 208 R180 WINDOW 0 47 75 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R8 SYMATTR Value 600 SYMBOL res -16 -320 M180 WINDOW 0 40 70 Left 2 WINDOW 3 37 41 Left 2 SYMATTR InstName R5 SYMATTR Value 100k SYMBOL res -16 16 M180 WINDOW 0 40 70 Left 2 WINDOW 3 38 43 Left 2 SYMATTR InstName R10 SYMATTR Value 100k SYMBOL OpAmps\\LT1058 112 -240 R0 SYMATTR InstName U5 SYMBOL OpAmps\\LT1678 752 48 R0 SYMATTR InstName U4 SYMBOL cap -80 -64 R0 SYMATTR InstName C3 SYMATTR Value 10n SYMBOL cap 1088 32 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C4 SYMATTR Value 10000n SYMBOL voltage 400 224 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value SINE(0 4 1000) SYMBOL cap 416 128 R180 WINDOW 0 24 56 Left 2 WINDOW 3 24 8 Left 2 SYMATTR InstName C1 SYMATTR Value 10000n SYMBOL res 832 -128 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 10k SYMBOL res 544 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R3 SYMATTR Value 10k TEXT -304 200 Left 2 !.tran 0 30 0 1u uic TEXT -304 152 Left 2 !.options plotwinsize=0 numdgt=7 method=trap TEXT -272 -568 Left 2 ;1kHz low distortion sinewave generator. TEXT -272 -536 Left 2 ;24 Jan 2025.

I never said it did. I was looking for comments on the way the current mirrors might screw up the waveform. I didn't get any.

Then you haven't looked at the current waveform going through the the FET.

And you'd probably better dump LTSpice 24.1 - it has been claimed that it has a serious bug. That might explain why your simulations of my circuit run a thousand times slower for you than they do for me and a couple of other people.

I never said you said it did. Facts are still facts whether anyone says them or not.

But I have looked at the distortion level both with and without the FET stabilizer and I have not found any difference worth having in an LTSpice simulation. In any case the current going through the FET also goes through the parallel resistor which, as you pointed out some time ago, should be as small as possible.

Perhaps JL would like to elaborate on what he means by two FETs in anti-parallel. How would you drive the gate of the other FET?

Could you please provide a reference to this claim. Who has claimed that it has a serious bug and is there an online discussion anywhere? Exactly what is this serious bug other than the fact that your circuit gets completely different results?

There is obviously a big difference but I have not so far seen any evidence to confirm that it is a serious bug.

"Bill Sloman" snipped-for-privacy@ieee.org wrote in message news:vnck1i$295d5$ snipped-for-privacy@dont-email.me...

LTSpice 24.1.1 is now available. The circuit below produces a 24mV pk-pk sineish wave at 23 MHz on my installation of LTSpice 24.1.1 with all component updates. FFT shows 23 MHz at -40dB Simulation speed is about 115 us/s I didn't simulate beyond 2.5 ms

Simulation in LTSpice 24.0.12 shows pretty much identical behaviour but the simulation speed is slower at about 75us/s.

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"Bill Sloman" snipped-for-privacy@ieee.org wrote in message news:vnck1i$295d5$ snipped-for-privacy@dont-email.me...

If U3 and U8 (LT1115) in your circuit are replaced with LT1678 then on my computer with LTSpice 24.1.1 and all component updates, the simulation completes almost as fast as I can start it, at about 55 ms/s. A sample near 10s is not quite 60dB down at 3kHz and 5kHz and 70dB down at 7kHz, approaching 80dB down everywhere else. The parasitic 23MHz signal has gone.

So the reason for the slow simulation speed in 24.1.1 is something to do with LT1115.

The circuit I simulated in 24.1.1 with LT1678 is below.

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tol=1 SYMBOL res -1696 -1344 R0 SYMATTR InstName R33 SYMATTR Value 18k SYMBOL npn -1584 -1424 R0 SYMATTR InstName Q5 SYMATTR Value 2N5089 SYMBOL npn -1296 -1424 M0 SYMATTR InstName Q6 SYMATTR Value 2N5089 SYMBOL OpAmps\\LT1678 -656 -1408 R0 SYMATTR InstName U3 SYMBOL OpAmps\\LT1678 -176 -1520 R0 SYMATTR InstName U8 TEXT -1736 -600 Left 2 !.MODEL BAS70L D IS = 3.22E-9 N = 1.018 BV = 77 IBV = 1.67E-7 RS = 20.89 CJO = 1.608E-12 VJ = 0.3891 M =

But your line does imply that I did, and that is a fact.

Then you haven't looked hard enough. Get LTSpice to plot the current through the FET minus the sine function current that ought to be running through it.

In any case the current going through the FET also goes through the parallel resistor which, as you pointed out some time ago,

That's not what I said, which you have clearly misunderstood.

The same way as you drive the gate of a single FET, from the error signal coming out of the rectifier-filter-integrator stage, but with opposite polarity and with a DC offset reflecting differences in the FET gate on-voltages (which have a fairly large production tolerance).

It call for a fairly elaborate setting up procedure and microcontroller and a DAC or two to make it work = loads of components.

My informant said it had come up on the LTSpice user's group, wherever that is.

Obviously there is, but I don't know where it is.

I'm not claiming that this is the result of the bug - whatever it is - just raising it as a possibility.

No surprise there.

The LT1678 looks like a nice part, but at $10 each it has to be. The application doesn't need a rail-to-rail op amp.

John May has pointed out to me that the LT1115 LTSpice model is just a variant of the LT1028 Spice model. I used the LT1028 in a rather demanding application some forty years ago and while it had its idiosyncracies, generating a 23MHz parasitic oscillation wasn't one of them.

The performance you are now getting sounds like what I've been seeing all along, and presumably reflects the defects of the current mirrors.

I've tried to improve them a bit but never got more than a dB or two of improvement. I need better insight. Talking to people often helps develop that but it hasn't worked here.