ethernet chips

What is fairly high speed? There is a broad range of ARM chips available with integrated ethernet + PHY (NXP has several choices). And why not handle the TCP/IP stack inside the main processor? The uIP TCP/IP stack

is very compact, complete and fast.

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Microchip has a very small device that can do both MAC and PHY, but it only works at 10Mbit/s and has an SPI interface. Freescale has a 16 bit microcontroller integrated with a PHY (I think it's a 100Mbit one, but I'm not sure). I don't remember the part numbers, but take a quick look at the vendor's sites and you'll find it.

Avishay

Something that doesn't dominate receiving, say, a 100-byte packet, crunching it, and sending a reply. Maybe being able to transfer a megabyte per second between the ethernet gadget and my application processor. The 240 kbaud Xport max is definitely painful.

There is a broad range of ARM chips

We use a 68332 in roughly a dozen applications, running lots of assembly code, to do stuff like waveform generation, thermocouple acquisition, tachometers, realtime stuff like that, mostly in VME modules. We could use the existing hardware and code practically unchanged if we add a second chip to manage the ethernet stuff. It's not a bad partition.

The Gridconnect chip will (apparently) allow our 68332 to directly address the receive and reply packet buffers as blocks of 16-bit memory, which is hard to beat for speed.

John

I doubt it is that easy. Some calculations like CRC and padding for short packets need to be done before a packet can be send onto the network. The gridconnect looks like a microcontroller with 2 embedded ethernet ports. From there you'll need some double buffer memory / fifo to get the data across. If you can live with UDP, you could get away with an FPGA design. UDP packets are easy to encode/decode. A MAC that drives an external PHY is not so hard to design.

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It comes with an RTOS and a tcp/ip stack, so we need only present the verified payloads to the 68K access port, not the ethernet overhead stuff. The idea is the the data payloads would magically appear in a block of memory that's part of the 68K address space. Apparently the

68K chip select could seize control of the gridconnect chip's internal ram whenever it feels like, and read/write it via a 16-bit data+address port.

That's a possibility, but we'd need an FPGA and a PHY, compared to the single Gridconnect BGA.

John

So, something like SPI would likely be okay?

That's a lot of SRAM.

Microchip's new PIC18F97J60 does 10-Base-T MAC and PHY with a reasonably capable CPU (10 MIPS). They have a 'free' stack. It's a fairly new part, so beware the errata.

There's also this 10Base-T SPI chip (ENC28J60):

.

Best regards, Spehro Pefhany

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The possibility to access the internal memory of the Gridconnect is a neat feature. Handshaking may be an issue. It seems the Gridconnect is not a bad solution *IF* the tcp/ip stack is not buggy/slow. Be sure to get the source code!

That's a good point. However, I doubt you can get away without glue logic and some synchronisation wait-states in the 68k.

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John,

I recommend the Si Labs CP2201 which includes integrated 10BASE-T PHY, MAC, royalty-free TCP/IP stack and has max interface speed of 30Mbps to another microcontroller. It's 5.88 at Mouser in qty. 1. I think you will find this solution more satisfying than the Microcheap. Good luck.

regards, Kadir "Solid Gold" Suleyman

You mean cheaper then those that cost you an ARM and leg? ;-)