Bus interfaces & FSMs

A question to all who have written a bus interface. Is a finite state machine the best way to implement a bus interface (e.g. ISA, PCI, uController) or does it matter. I have examined a few and almost everyone is a FSM. I haven't written any FSMs to date and was curious if there was a benefit to using an FSM. Does it reduce the logic needed in the design, or does it allow for a faster design? Any comments are appreciated.

I have done a few bus interfaces myself, but due to my lack of experience with a FSM I have not their use in the applications.


Reply to
Jason Berringer
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Well, when I wrote an OPB->ISA bus bridge I used FSMs for both bus=20 interfaces. A FSM makes it quite simple to achieve operation according=20 to the bus specs due to its sequential nature. I didn't look into other=20 methods though so I can't say a FSM is the best solution. Any basic book =

on VHDL/Verilog, or the Xilinx docs for that matter, should give you=20 hints on how to code a state machine.



----------------------------------------------- Johan Bernsp=E5ng, snipped-for-privacy@xfoix.se Research engineer, embedded systems

Totalf=F6rsvarets forskningsinstitut Swedish Defence Research Agency

Please remove the x's in the email address if replying to me personally.


Reply to
Johan BernspÄng

"Jason Berringer" wrote

First of all: what doi you consider to ba e FSM and what to be no FSM? You won't be able to implement a bus interface without any kind of statemachine if you consider a counter to be a statemachine. I would use a dedicated FSM to get a reusable structure with easy debugging abbilities (if your timing and area needs allow you to use one).

bye Thomas

Reply to
Thomas Stanka

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