Basic FPGA question about Reset

As other people have pointed out, you can specify the initial-state of any flop, using a VHDL-attribute, or a Verilog 'initial' statement.

Verilog-2001 version:

wire my_one_shot_reset; // active-high reset (fires once at FPGA-config/powerup!) reg [15:0] my_one_shot_ctr = 0;

always @ ( posedge clk ) begin : always_my_one_shot_ctr if ( my_one_shot_ctr < 10000 ) my_one_shot_ctr Hi

Reply to
aka
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What did the power look like for the case that failed?

I'd expect an external power-watcher chip would get OR-ed in with the internal logic so you would have the best of both worlds. What went wrong?

Actually, now that I look more carefully, things get complicated.

Is figure 23 in the Spartan3 data sheet the whole picture?

Are there restart paths not shown to handle power-not-good (as detected by internal logic) while configuring?

What if PROG goes active during configuration?

What happens if INIT goes low after configuration has started? It gets forced low by a bad CRC. It would be handy if that restarted the whole thing if you are configuring several devices on a chain.

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Reply to
Hal Murray

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