As other people have pointed out, you can specify the initial-state of any flop, using a VHDL-attribute, or a Verilog 'initial' statement.
Verilog-2001 version:
wire my_one_shot_reset; // active-high reset (fires once at FPGA-config/powerup!) reg [15:0] my_one_shot_ctr = 0;
always @ ( posedge clk ) begin : always_my_one_shot_ctr if ( my_one_shot_ctr < 10000 ) my_one_shot_ctr Hi