Google dug up the following quote from Ray back on 2003-04-21.
/quote
I got nailed on an early Virtex design where the 1x and 2x clocks were sourced by the same DLL. Several factors contributed:
- the 1x clock was very lightly loaded while the 2x clock was heavily loaded,
- There was fair amount of jitter on the clock input (>300ps IIRC),
- There was heavy output switching on pins adjacent to the clock input pin (adds to jitter at DLL clock input)
- the failing nets were on direct flip-flop to flip-flop connections (no LUT) on FF's that were floorplanned to be adjacent.
- static timing indicated no setup or hold violations.
The combination of the jitter (which with input jitter barely in spec plus jitter introduced by output current modulation of input thresholds was likely out of spec), highly skewed loading (not convinced this is a real factor), and the absolute minimum flip-flop to flip-flop delay conspired to bite us where it counted. Since then, we have as a policy treated the 1x and 2x clock domains with utmost care to make sure the receiver is not sensitive around the transmitter's active edge. I suspect that if you have no direct connects between adjacent slices at the clock domain boundary, you won't have a problem.
/unquote
Peter & Austin, I really want to believe you. Do you think Ray's being overly careful? Could it be a problem in the "extreme" topology Ray describes?
Jeff