FPGA.
insane
Mbits ???
...and if that magic word happens to appear before the "correct" one? It's
*bad* engineering practice to depend on magic words. As I said, I've seem more than one rookie gigged by such dumbass mistakes....and you open yourself to the problem I describe above; *BAD* plan.
Its not a bad plan. Just add a few gates to control the clock and data so the FPGA only sees the data it needs to see. I've used this method and it works excellent.
-- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------
That's not what he's advocating.
parts
flash
FPGA.
insane
Mbits ???
by
It only takes one wire from the uP to the FPGA to hold the FPGA reset until you're ready to stream the config data.
John
real
parts
flash
FPGA.
insane
Mbits ???
is
internal
by
Again, that wasn't fonz' intention. He proposes to use the FPGA's config sync word as the delimiter. It might even work, during debug.
t in real
face parts
rial flash
es the FPGA.
mething insane
l 30 Mbits ???
AM bit is
t help a
RLL
dn't get
internal
ll not
Altera
out 15.
fective.
,cheap,
ng to
gh the
nd the
ig
gthan one gigged by
=A0It's
seem
fig
take the standard dataflash the read command is 0x03 and three bytes of address that is 32bits
how could those 32 clocks in any possible way produce the 64bit sequence at the start of a config stream?
-Lasse
real
parts
flash
the FPGA.
something insane
Mbits ???
bit is
help a
get
internal
not
Altera
effective.
cheap,
the
the
gigged by
I've seen an 80 byte SOF record do the same.
port in real
terface parts
serial flash
gures the FPGA.
something insane
all 30 Mbits ???
y RAM bit is
sn't help a
se RLL
.ouldn't get
zed internal
:1.
will not
the Altera
about 15.
effective.
GA,
tly,
are cheap,
going to
rough the
a and the
onfig
nfig
ed
re than one gigged by
n? =EF=BF=BDIt's
aid, I've seem
PGA's config
if 32 bit becomes 64 something is seriously broken and you can't even read the flash correctly so no matter what you do it won't work
-Lasse
Ahh. That wasn't clear to me.
During development of JTAG programming routines for Xilinx FPGAs I smoked at least one FPGA. AFAIK the chances for something going are very small though because the frames also contain a CRC checksum. I also doubt missing the first frame is a problem since the start of the data consists of a few dummy frames to synchronize the FPGA to the datastream.
-- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------
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