AI for FPGA design

Dear Mister Larkin:

Ben Cohen posts many LinkedIn posts via which he promotes Perplexity AI for helps with Verilog - not to avoid Verilog.

A lady claims via LinkedIn that an AI service produced a bad Verilog code, so she concluded that an AI is not going to threaten her job, and I wrote to her that she deserves a refund.

Then why produce Verilog code?

Then why produce Verilog code?"

Dear Mister Larkin:

Well, I favor VHDL! However, as for Ben and an AI, Ben reports that an AI= =20 makes mistakes. I suggest reading what he writes about it.

True. Programmers should write everything in hex code, rather than using the crutch of assembler or some even higher level language.

It wouldn't help their productivity, and it would make it even harder for the people maintaining the product to work out which segment of code or chunk of logic was actually doing what, but at least you know what's actually going on, even if you can't work out what it was intended to be doing, or why.

Hmm.

On Mon, 11 Aug 2025, Edward Rawde wrote: "> Ben Cohen posts many LinkedIn posts via which he promotes Perplexity AI

Dear Mister Rawde:

Thanks for exposing this shortcoming. I will inform Ben.

On Mon, 11 Aug 2025, Bill Sloman wrote: "On 11/08/2025 6:32 am, john larkin wrote: [. . .]

True. Programmers should write everything in hex code, rather than using the crutch of assembler or some even higher level language."

Dear Mister Sloman,

I believe that what Mister Larkin is getting at here, is that he wants to use an AI at a higher level than Verilog, so Mister Larkin is perplexed as to why Ben Cohen advocates an electronics worker to both use Perplexity AI to produce Verilog code and to continue manually writing in Verilog.

I wrote yesterday: "A lady claims via LinkedIn that an AI service produced a bad Verilog=20 code, so she concluded that an AI is not going to threaten her job, and I wrote to h= er that she deserves a refund."

Dear all:

"User Agreement Effective on November 20, 2024 [. . .]

1. Copy, use, display or distribute any information (including content)=20 obtained from the Services, whether directly or through third parties=20 (such as search tools or data aggregators or brokers), without the=20 consent of the content owner (such as LinkedIn for content it owns);" says
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I asked Ms. Sharada Yeluri for permission to republish from that LinkedIn= =20 thread. She likes this question, so I republish . . .

"Sharada Yeluri =E2=80=A2 3:e+Premium =E2=80=A2 3:e+ Engineering Leader

F=C3=B6lj [Follow]

ChatGPT o1 with advanced reasoning=E2=80=A6 excels at competition-level mat= h,=20 solves PhD-level science questions, tackles complex multi-step problems=20 with chain-of-thought reasoning=E2=80=A6 The list goes on.

Curious about its prowess, I decided to test its ability to develop=20 Verilog RTL code for a functional block that=E2=80=99s commonly found in mo= st=20 networking and XPU ASICs: a buffer manager. After all, they charge $200=20 per month, so there must be some magic.

Grudgingly, I paid the fee and posed a challenge: Build a buffer manager=20 for a 16K entry-deep buffer that is 128 bits wide, shared dynamically=20 between 256 queues. The module should sustain one enqueue and one dequeue= =20 every cycle without stalls... Use SRAMs for linked list structures, and=20 yes, the SRAMs have two-cycle read latencies...

I know there aren=E2=80=99t many open-source Verilog designs for hashtag#Ch= atGPT=20 to learn from. Still, with its "advanced" reasoning abilities, I expected= =20 a decent output.

It churned out an RTL module and a Verilog test bench=E2=80=94points for ef= fort.=20 When I pointed out how the design could not handle back-to-back dequeues=20 from the same queue, it gave up too quickly and declared there was no way= =20 to design it without stalling the inputs. I nudged it towards approaches=20 like doubly linked lists or ping-pong buffers. It understood the concepts= =20 and even explained them back to me, like a student trying to impress a=20 professor... =F0=9F=98=8A

When the RTL didn=E2=80=99t give the correct results, I directly fed back t= he=20 simulation results from its test bench for it to analyze. After a few=20 feedback iterations, the enqueues started working=E2=80=94progress!

The dequeues, however, remained stubbornly broken. Hoping to simplify=20 things, I relaxed the constraints, allowing a 5-cycle gap. No luck...=20 Instead, ChatGPT decided the simulator was wrong=E2=80=94an audacious claim= for=20 an AI model still learning to count pipeline stages.

Eventually, I debugged the RTL myself and found the culprit - a typo.=20 After fixing it, the dequeues worked. However, the design still lacked=20 hazard checks for back-to-back dequeues, and after an hour of trying to=20 teach pipeline bypasses, I called it quits.

The good news? =F0=9F=A4=94

While the ChatGPTs and copilots might take over sw engineer jobs, they=20 are far from snatching jobs from ASIC engineers=E2=80=A6 =F0=9F=98=8A

They may argue about the lack of open-source Verilog for AI models to=20 train on - chip designs are locked away tighter than bank vaults. But if=20 ChatGPT can solve Olympiad math through reasoning, why does reasoning=20 through pipeline hazards feel like rocket science to it? =F0=9F=A4=94

The pace of innovation needed to achieve hashtag#AGI is directly tied to=20 advancements in XPUs and the networking hardware they rely on. If AI=20 companies are serious about accelerating AGI development, we need models=20 that can reason through complex chip design problems and help compress=20 design cycles. After all, these chips are the foundation for their AGI=20 dreams.

hashtag#OpenAI team, now that the Olympiad math is behind you, how about=20 the chip design challenge next?"

"Sharada Yeluri

F=C3=B6rfattare [LinkedIn Original Poster] Engineering Leader

Andreas Olofsson, 100% agree. But again, the idea behind reasoning models= =20 is that they work well even in the absence of tons of data during=20 training. The model seems to understand all the Verilog syntax and can=20 spit out hundreds of lines of code that compiles well. when I explain=20 pipelining concepts, it understands and repeats back it's interpretation=20 with examples. It almost felt like I was talking to a new college grad.=20 But, it fell short of actually implementing the concepts back in Verilog.= =20 It probably needs fine-tuning during the training phase with examples=20 where the feedback from the simulation can be used to train the models.=20 Just thinking out loud."

"Sharada Yeluri

F=C3=B6rfattare Engineering Leader

Gaurav Vaid , hmm.. interesting thoughts."

"Sharada Yeluri

F=C3=B6rfattare Engineering Leader

Rob Sprinkle, I haven't used Haskell personally. So, I won't be able to=20 comment on it. I think the quality of the code improved a lot from the=20 first pass to when I finally jumped in. It actually does learn when you=20 teach new concepts. For example, when I told her that the pipeline names=20 were all messed up and it should use strict suffixes like _p0, _p1, etc.=20 to distinguish between the pipeline stage signals, it rewrote the code so= =20 well that it eventually made it easy for me to debug. If we have to=20 intervene from the beginning, it defeats the purpose IMO.."

"Sharada Yeluri

F=C3=B6rfattare Engineering Leader

Ivan Djordjevic , reasoning models, as claimed by openAI, are supposed to= =20 be more intelligent than parrots :)"

"Sharada Yeluri

F=C3=B6rfattare Engineering Leader

From=20Open AI: " The models use a sophisticated chain-of-thought reasoning= =20 process, allowing them to break down intricate problems into manageable=20 steps." My experiment aims to see if the model can solve the problem on=20 its own. Even then, I broke it down step by step, simplified the problem=20 several times, asked it to reset and start over, etc., but I just could=20 not get it to solve pipeline hazards. If you have better luck, do let me=20 know."

"Sharada Yeluri

F=C3=B6rfattare Engineering Leader

Varun Uniyal I don=E2=80=99t think chipNemo can solve this. But I could be = wrong.=20 Try ir out=E2=80=A6"

"Sharada Yeluri

F=C3=B6rfattare Engineering Leader

Rajesh Parikh, Great thoughts. Maybe, in addition to more data during=20 training, these domain-specific models also need access to verilog=20 simulators and test benches written by either humans or other models=20 during training, as well as inference."

"Paul Colin Gloster =E2=80=A2 Du [Thou in Swedish - i.e. I] Researcher at Universidade de Coimbra

Dear Sharada Yeluri: Happy New Year! Demand a refund!" She finds this=20 comment to be funny. I seriously mean it.

"Sharada Yeluri

F=C3=B6rfattare Engineering Leader (redigerat)

Debajyoti Pal, I understand your concerns. But think about it this way:=20 around 35-40 years ago, people used to hand-draw the schematics of logic=20 gates for their chips. There was no concept of using an EDA tool to=20 synthesize the gates. When the EDA tools came out, a lot of design=20 engineers protested that the tools did not know how to come up with an=20 area-efficient netlist that also meets timing and argued that we should=20 still rely on hand-drawn logic gates for high-speed datapath. I remember=20 at Sun Microsystems, we used to have special teams to do datapath design=20 where the logic to gates was done manually, and engineers did manual P&R.= =20 Gradually, as the tools became better at what they do, we started=20 trusting them for all digital logic design. The reason the tools got more= =20 advanced is that EDA vendors built feedback systems where the timing is=20 fed back to make the synthesis and P&R better. LEC and formal methods=20 ensured that the netlist is functionally equivalent to RTL, etc. I see=20 the same transition that will eventually happen again, with tools=20 generating RTL from high-level specs using advanced reasoning and humans=20 using other verifier tools to ensure the generated RTL can be used. It is= =20 a matter of when not if. IMO"

"Sharada Yeluri

F=C3=B6rfattare Engineering Leader (redigerat)

Dawei Wang, Nice to hear from you. I did what you suggested to some=20 extent. The Verilog-based TB and RTL are both generated by ChatGPT, and I= =20 was feeding back the result from the TB as is to ChatGPT so that it can=20 fine-tune the RTL until it works."

"Sharada Yeluri

F=C3=B6rfattare Engineering Leader

Raja Ramkaran Reddy Rudravaram, Thank you. Yes, I will try the RAG one=20 next."

"Srinivas Lingam, thanks. I agree that model developers haven't yet=20 focused on enhancing the model's capabilities for chip design challenges.= =20 Most are probably giving up too soon with the excuse that they can't find= =20 enough data. Even with limited data, can the model developers use the=20 same RL techniques they have used for math to improve the models for RTL=20 coding? Could they use Verilog simulators as verifiers during=20 post-training fine-tuning? This, combined with agentic workflows (where=20 the generated RTL is continuously checked with simulation by the agents=20 and fed back to the model until it converges), could probably yield good=20 results. I hope to see more innovation on this front."

"Sharada Yeluri

F=C3=B6rfattare Engineering Leader

Saurabh Chakraborty , did you try this challenge?"

"Paul Colin Gloster =E2=80=A2 Du Researcher at Universidade de Coimbra

Dear Mister Patrick Lehmann: Demand a refund! Limited LinkedIn does not=20 allow having more than one reaction icon set. I set that comment by you=20 to insightful, and I also want to set it to funny!"

"Sharada Yeluri

F=C3=B6rfattare Engineering Leader

Sreenivas Nandam It is not a syntax error. It has one extra pipeline for=20 the valid bur, not for the address, so it could never correctly line up=20 the read data with the requester. For some reason, it was not able to=20 figure that out."

john larkin snipped-for-privacy@glen--canyon.com spake the secret code snipped-for-privacy@4ax.com thusly:

What about HLS?

That may be what he has in mind. He's not a subtle thinker, so he may have missed the point that artificial intelligence isn't entirely reliable, so the code it produces may not always work the way we'd like it to.

Human designers have the same weakness - it often comes from having to solve imperfectly specified problems.

Most of the requests for help we get here generate a lot of "what are you actually trying to do" questions.

A good bit of real life electronics involves looking at other people's imperfectly document designs and working out how they were intended to work, and why they went wrong in some specific unforeseen situation.

I'm not perplexed. I just think that there will eventually, maybe soon, be better ways to design FPGAs than trying to define parallel structures with hacked procedural languages.

It's the typing vs soldering thing again. Words vs images. Parallel execution every clock vs the idea of a program counter executing at some one location in a sea of object code.

When FPGAs were new, we designed with schematics. I design FPGAs on whiteboards now and let other people type the VHDL and do the test benches. I suspect that's a common procedure: visual people design architectures and verbal people type it in.

LabView is awful, but something like that could design FPGAs.

The benefit of an intermediate VHDL/Verilog step would be code portability.