OpAmp design - from theory to practice

Here's the really short, over-simplified version that glosses over what could be a year-long senior/graduate-level class at a university:

For GBP and phase margin, model the op-amp as a perfect differential amplifier followed by a transfer function, i.e.

Vout = (V+ - V-) * (2 * %pi * GBW / s)

You may need to make your transfer function more complicated than this if the DC gain or the exact phase margin is important, but I hope you see where I'm going.

For things like input bias current and input bias voltage (if that's even important on an OTA), model the thing as an "ideal" part with voltages or currents injected into the relevant portions of the circuit.

For things like slew rates and other nonlinearities, either simulate and check that the nonlinearities aren't excited (i.e., the slew rates are never exceeded), or that the nonlinearities don't have much effect (which is pretty much what you have to do with crossover distortion).

--
Tim Wescott 
Control systems, embedded software and circuit design 
I'm looking for work!  See my website if you're interested 
http://www.wescottdesign.com

Just to _really_ throw a wrench into the works: -to-frequency is an old idea that's mostly gone out of favor because of advances in digital processing and in ADC converters. If I were on your team I would be questioning the system-level decision to continue using it -- but I'd be ready to back off from that if there's good reasons to stick with it.

--
Tim Wescott 
Control systems, embedded software and circuit design 
I'm looking for work!  See my website if you're interested 
http://www.wescottdesign.com

Hi Tim,

thanks a lot for the answer, first of all!

As I said, not an expert; I am not really sure what is the message you are trying to convey here, so I can give you some more details:

- we are designing a custom ASIC because discrete components cannot withstand the expected level of radiation (target is 10kgy in 20 years and probably more)

- given that, we cannot use FPGAs either! the ASIC must operate "standalone" and using basic components only (all validated for radiation hardness, of course)

- starting from this, I don't really see other solutions. I mean, maybe a self-switching, multi-range CFC might not be the best option (Sigma-Delta? pipeline?) but we have an input current and we need to digitize it, there is no escape from that :)

Thanks also for the other answer, of course.

Since you are not the first person giving me that answer, I am starting to wonder if my question is simply a non-question, because I am still left with my doubts.

Oh well, I'll keep studying I guess :)

thanks again!

Francesco

We used to do it that way to bodge an analogue only high range onto what was originally designed as an ion counting system using the existing backend which was similar to an HEP multichannel analyser. It didn't do the detector much good lifetime wise but it sold more kit.

Can the device not be shielded with lead foil to some extent?

This although now very dated might give you some inspiration as a starting point for a suitable current to frequency design:

Mass spectrometers Faraday cups often do a high gain stabilised current to voltage conversion and then digitise the resulting voltage. This leaves you with thermal drift, gain stability and zero level problems.

--
Regards, 
Martin Brown

CT scanners for medical x_ray use the current to frequency method at a similar current range. Off the shelf parts are available and many papers have been published, so that might be a place to start.

S.

I do not see the direct connection between cf converters and FPGAs, but FPGAs can be used in a radiation infested environment. I just have designed a few. You'll need to make registers, counters, RAMs triple module redundant, but you need that in your custom chip also. The contents of a RAM cell or flipflop that is hit is lost, even hard wired gates can malfunction for some time.

Even voltage regulators that are hit can go berserk for a few milliseconds. Be sure to have enough output capacitance so the regulator cannot kill everything while it is delirious.

I have made a nice library that looks like std_logic / std_logic_vector and that hides most of the nasty triple module redundancy details. No, it is not available.

In RAM-based FPGAs like our prehistoric Virtexes is the additional complication that the configuration is stored in RAM and that is vulnerable. So, the config ram must be reloaded on a regular base from the external ROM while the chip is running. That can be done but it is a nasty thing to do, especially if the scrubber logic is on the chip to be scrubbed.

You also cannot use distributed RAMs in the Xilinx case since that are really small parts of the configuration ram made accessible to the user. Our software lady found out that her Picoblaze registers would auto-clear all few minutes. Turned out that it uses a distributed RAM for its registers and that was overwritten by the scrubber. But it proved at least that the scrubber works.

I could heal that by patching the Picoblaze to use solid flip flops instead of the 16 bit RAMs. :-)

regards, Gerhard

[cut]

Hi Gerhard,

thanks for the answer.

I will give a general answer valid also for the others that commented on ra diation hardness: we are operating with a 7 TeV beam of protons (you might guess where I am working, at this point :D) and the radiation areas are *ve ry* harsh. This is not a problem that can be solved just by shielding or so me smart tricks (but we are diverging from my question).

People way smarter than me tell me that no FPGA can withstand that kind of radiation for a reasonably long amount of time.

The comment on the FPGA was just meant to say that I cannot mount in the pr oximity of the chip I am designing an FPGA to control it. Nothing more than that; you are right when you say that a CFC and an FPGA have nothing to do with each other :)

thanks

Francesco

It was really simple: you said you aren't an expert, that you're revamping an old design, and then you proposed a method that has been superseded by current-to-voltage followed by ADC in many places. That made me think that maybe there's a better approach.

This doesn't mean that I'm convinced that you should change approaches -- perhaps current to frequency is best, or at least changing from that to some other method would require to many changes elsewhere in the system for it to be viable.

'K. So that affects whether or not a local ADC is a reasonable thing to consider.

I never suggested an FPGA.

If you have the bandwidth for the data, using a sigma-delta modulator on the front end may work better -- just output raw or only lightly processed bits from the 1-bit ADC, and do the actual processing somewhere at a lower radiation level.

I'm thinking like a system-level engineer, and part of that job entails re-thinking previous assumptions. I'm always confused at this stage of a project, or at least find myself faced with more choices than I'd prefer.

Basically, at this stage, you do some feasibility studies of each approach, and ask yourself which ones are better. Since you're doing an upgrade of an existing system, you want to give a lot of weight to what's already there.

And it sounds like you're a junior member of the team, so someone else may have already thought of all of this and either determined from first principles that the current approach is best, or they're married to it and won't budge even if it's the worst. So at your level you may not get to make the decision to change at all (but if you think some other approach might be better you should prepare your mind to not be dismayed by any answer, and then ask).

--
Tim Wescott 
Control systems, embedded software and circuit design 
I'm looking for work!  See my website if you're interested 
http://www.wescottdesign.com

There are not many rules out here anymore :-)

Your English looks very good (I am non-native myself).

130nm isn't considered very new these days but, of course, for radhard your selection will be limited. New designs are still done in the larger geometries. The most recent one I was involved in was 300nm.

Do you have a link where this paper can be accessed without charge? From non-subscribers they want about $40 just to take a look.

1nA gets you into noise floor issues with the first stage if the integration window means >20kHz bandwidth.

Usually the first stage needed would be a transimpedance amplifier or TIA, in other words a glorified current to voltage converter, followed by a V/F conversion or another more modern method. Phil Hobbs here in this group is the guru on low noise TIAs, maybe he could chime in.

It might also help to talk to these guys:

--
Regards, Joerg 

http://www.analogconsultants.com/

I assume then that you are abt. 2 or 3 hours by car from me in the south/western direction.

Yes, if the FPGA gets warm from the radiation, that won't work. :-) But good enough for space probes or devices on the ISS. After all, there live some people. SEUs happen there, and it's bad if you lose the counter that has yourtime/position in orbit. But it surprised me that even robust things like voltage regulators are affected.

cheers, Gerhard

radiation hardness: we are operating with a 7 TeV beam of protons (you migh t guess where I am working, at this point :D) and the radiation areas are * very* harsh. This is not a problem that can be solved just by shielding or some smart tricks (but we are diverging from my question).

f radiation for a reasonably long amount of time.

proximity of the chip I am designing an FPGA to control it. Nothing more th an that; you are right when you say that a CFC and an FPGA have nothing to do with each other :)

If you are at Cern, I would think there are many people there who know more about your problem, than we do here... where's Jeroen Belleman?

George H.

The old triode pass tube -> error amplifier tube with neon lamp in the cathode makes a great rad-hard voltage regulator! Pummel it with gamma all day long, it don't care. Neon lamps are especially resilient.

Little power-hungry, though.

Thanks! That helps a great deal. The SNR numbers in there do not look very stellar but they claim to have achieved all objectives stated (using sub-ranging though).

Francesco, I am wondering what you'd like to improve above and beyond what these guys did? Is it the sub-ranging and subsequent SNR trade-off that you don't like?

If you really want to use a I/F concept (which as others have hinted may not be the optimum here) there are V/F converters where the manufacturer claims 6 decades which corresponds to 120dB:

This would have to be preceded by a low noise TIA for a current to voltage conversion and those architectures are described in the field of pre-biased photodiodes. Like here:

--
Regards, Joerg 

http://www.analogconsultants.com/

Even space-rated ones?

I found the old uA723 to be of cast-iron behavior in nasty environments but I don't know about its formal radiation tolerance.

--
Regards, Joerg 

http://www.analogconsultants.com/

I'm not an IC designer, but I used to pal around with some. First you need to do the chip on a SOI process and not bulk. Second, use processes with wider features by preference.

I-to-F is actually reasonably nice, since it uses time and frequency and is immune to voltage offsets. Much better than V-F.

Cheers

Phil Hobbs

The documentation of the ST RHFL4913 & friends mentions exactly this, including the workaround with the large output capacitors.

cheers, Gerhard

You are right. Many experts around. Sadly, everyone is busy and I am not in direct contact with them on a daily basis, so it is difficult to get some collaboration going. But we are working on it :)

Francesco

Hi Tim,

[cut]

thanks a lot for the tips!

The choice of whether changing approach or not is also due to time constraints.

But anyway, thanks for any suggestion so far!

Francesco