Hi, there:
I am using Virtex-2 to do a partially reconfiguratable design. My two reconfigurable modules depend on muxed clock buffers and DCMs located in the area group of a fixed module.
During active modules implementation, some of the wires on the BUFGMUXs and DCMs were routed, while the other wires for example the vcc_fake on the Bus Macros were not! Is this the correct behavior? In the two reconfigurable modules implementations, do I expect these routed & unrouted wires to be exactly the same?
Besides that, the file size of the bit-streams of two reconfigurable blocks were not the same, is this correct?
Does the BitGen for active module implementation ONLY generate bitstream for my AREA_GROUP or the routed wires on BUFGMUXs and DCMs also?
Thanks for your answers.
Best Regards, Kelvin