ESR homebrew revisit ? good design ?

Thanks to all for the ESR meter advice.

I had settled on building this *free* ESR meter schemat ...

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however something troubled me about the schematic

Almost everyone alluded to ESR meters using some pulse/wave/function passing through CAP to determine the ESR.

and this plan does not appear to have a pulse/wave/function being fed through the test CAP or am i missing something ?

so is this ESR meter really an ok->good ESR plan ?

If it is not obvious i am looking for cheap (free) ESR schematic/plans to build

thanks for any helpful replies, robb

Reply to
robb
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IC1-B is a "square wave" oscillator. Since there are no values on the drawing, no way to determine the intended frequency and duty cycle of the oscillator.

--
Dave M
MasonDG44 at comcast dot net  (Just substitute the appropriate characters in the 
address)

"In theory, there isn't any difference between theory and practice.  In 
practice, there is."  - Yogi Berra
Reply to
DaveM

being

on the drawing,

the oscillator.

Thanks DaveM,

Ah ..... of course the omnipotent (well versatile, as i am learning) opamp. I knew i must be missing something as someone said this schemat is not too bad.

i only made it about three pages into the datasheet originally but when i read your reply i went to page 19 there was an exmple of using as an oscillator.

thanks Dave for the help, robb

Reply to
robb

IC1-B is a square wave generator due to the hysteresis design with the feed back to the (+) input. C3 makes up for the timing frequency used.

The circuit is using the raising edge of the square wave as the time domain for acquiring readings. Initial raise will only be seen in the IC1-D circuit due to the small size of C4. R7 will discharge it quickly.

In the bridge it self, if the Test cap has some (R) in it, R9,R9 will not be at abs 0 volts. The offset is quickly reproduced and amplified via the IC1-C. Because this is the starting of the square wave from the generator, C4 will see a sharp raise in the signal and thus C4 being small like it is, will produce a nice short pulse of the amplitude that translates to an ohm reading via the IC1-D. After this initial starting pulse, there will be a continuous reference as a ramp how ever, this will have little effect. A perfect cap with 0 ESR, should never allow the sharp raise of the generate be seen at C4. All you should get is a 0 to 4.5 volt ramp at best. But in a cap that has some ESR, the starting ramp will not be at

0(R9+R10) and this is where the IC1-C will amplify it greatly at the same time the initial raising of the square wave. DS3 anc C6 will simply hold a reference for you, between cycles.

I know that is long winded but I think at times it's needed.

--
"I'd rather have a bottle in front of me than a frontal lobotomy"

"Daily Thought:

  SOME PEOPLE ARE LIKE SLINKIES. NOT REALLY GOOD FOR ANYTHING BUT
  THEY BRING A SMILE TO YOUR FACE WHEN PUSHED DOWN THE STAIRS.
http://webpages.charter.net/jamie_5"
Reply to
Jamie

Assuming I did the math right, IC1-b is producing ~ 95 kHz into the bridge via TR1 & 2, which is about what is claimed (100kHz) in the write up.

You can go here to see how the op-amp is configured and the frequency computed:

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The circuit works well, and is real easy on the wallet.

Ed

Reply to
ehsjr

being

formatting link

Tanks Ed, I am amateur occasional electronics hobbyist trying to learn more.

i expect this to be quite easy on my wallet as i plan to use all salvaged components,(because it makes it more interesting for me) i have found all the components i need on a modem/hard drive controller /video card boards now for the even more fun part....

thanks for help, robb

Reply to
robb

How will you check the caopacitors then ? :->

Thanks to everyone for the interesting thread. I think i'll have a look a building one just for fun.

Cheers

--
Mitch

terminal_crazy@sand-hill.freeserve.co.uk
www.sand-hill.freeserve.co.uk/terminal_crazy
Reply to
Terminal Crazy

On a sunny day (Tue, 25 Dec 2007 10:19:46 -0800 (PST)) it happened gearhead wrote in :

It is not the frequency, it is the rise time of the square wave. If the wave rises in 1 femto second, the frequency can still be 1 Hz only. For a capacitor, to charge in a short time the formula Q = C x U = i x t shows that the voltage across the cap is U = (i x t) / C For normal values of 'i' and very short 't', U will be close to zero.

A typical example:

1 uF, 1 us time, 1 mA, then after 1 uS the voltage across the cap will be: U = 1 mA x 1 uS / 1 uF = 1 mV U = .001 x .000001 / .000001 = .001 V

For a circuit like this:

Uin ----- C ------- out | R1 | ///

For an input voltage change like this: ________________________________________ | | | | _|

The voltage across the resistor will look like this:

peak = Uin |\ | \ | \ | \ _| \_________________

If the capacitor has internal loss in th2 form of a resistance for example, then there is a voltage divider, and the circuit looks like this:

U in ---R2 - C ------- out | R1 | ///

The peak output is now no longer Uin, but R1 / (R1 + R2) x Uin.

peak = Uin x R1 / (R1 + R2) |\ | \ | \ _| \_________________

Reply to
Jan Panteltje

On a sunny day (Tue, 25 Dec 2007 12:55:26 -0800 (PST)) it happened gearhead wrote in :

You mean to R?

If the cap is inductive is is also defective :-) Some rolled foil caps, where the contact on the side of the foil gets lose, can make inductors. The circuit detects series 'impedance' in a sense. In a good capacitor series impedance is close to zero.

Reply to
Jan Panteltje

Hi, Robb -

I used SPICE to simulate the important parts of the circuit composed of the bridge and IC1-C and IC1-D. I used a pulse generator rather than IC1-B. I used voltage-controlled-voltage-sources rather than op-amp models. I looked up an arbitrary capacitor's ESR for this simulation.

I got the following output "indications" vs capacitor (arbitrarily 100uF) ESR:

ESR (ohms) Indication (percent)

0 100 .018 100 (specified value) .18 99 1.8 92 18 52 180 7

A 10uF with 0 ESR also indicated 100%.

So, the circuit appears to work, but it depends on what you are expecting from it as to how well it works. If you decide that anything below, say, 50% is bad, you may not catch the capacitor that causes equipment to fail when it has more than 1.8 to 18 ohms of ESR.

I think the amount of ESR that can be tolerated will depend on the target equipment's sensitivity to ESR. In some cases, you may find that even 1.8 ohms causes malfunction. In other cases you may find that 1K ohms of ESR causes no problems.

To verify the simulation, you could build the meter and test various capacitors known to be new and good. Then add some series resistance to each and record the readings. Then all you would need is experience to know when equipment will fail due to high ESR.

Cheers, John

Reply to
John

On a sunny day (Tue, 25 Dec 2007 22:11:21 -0800 (PST)) it happened gearhead wrote in :

Right, and it uses a peak detector approach, so the slowly decaying waveform part is not used.

OK, after posting the previous reply, it occured to me I could have misunderstood the remark about inductive. Indeed, if you used an almost infinite fast rising edge, any inductance, even the capacitor leads, would be seen, and a cap could be rated bad, while it actually was not. In this circuit however, the pulse comes from the output of an opamp oscillator, and those have reasonably slow rise times, micro seconds rather then femto seconds, and so we do not have to worry about very small inductances.

Indeed there is a useful range of capacitor values where it will work. I think the ESR meter, in this case, is mainly used for electrolytic capacitors, so maybe from 1uF up?

Yes, I think we agree here.

Reply to
Jan Panteltje

all

:->

haha..

i was planning use the Sam Goldwasser method with a function generator and oscope which is also talked about in a Buchsbaum book as well.

have a look a

very interresting to me as well.

robb

Reply to
robb

happened gearhead

:

Thanks Jamie, Jan and Gear,

thanks for the volley, i always seem to learn more when i read the relative experts volleying an idea around.

robb

Reply to
robb

[trim]

composed of the

than IC1-B. I

models. I looked

(arbitrarily 100uF)

expecting

below, say, 50%

to fail when

the target

that even 1.8

ohms of ESR

various

resistance to each

to know when

Thanks for the info, help and effort John,

I would try something like a simulation if i did not already have a hobby workbench overflowing with projects/ideas etc...

This ESR project fell out of another (in-complete) vintage microcontroller project i was working on. That was put on hold because the ever important ROM was fried and i am trying to locate a source for a ROM image and in the meanwhile trying to see if a could not engineer a new 8051 application to replace the original ROM program.

hobbying really does eat up alot of time, thanks again for your help and reply, robb

Reply to
robb

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