zero latency context switch - The Best Methods !!

Hi,

What could be the best method to achieve zero latency context switch between two processes ?

Thx in advans, Karthik Balaguru

Reply to
karthikbalaguru
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Two processors, running each process in parallel. There's _always_ some latency when performing a context switch. The absolute minimum would be a single clock cycle but that isn't instantaneous. Interrupts aren't instant for this very reason.

So, time to modify the question. What's the maximum latency that would be acceptable? You can work backwards from that.

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Reply to
Andrew Smallshaw

Ammiravo la mia cresta allo specchio quando karthikbalaguru ha detto :

As Andrew Smallshaw just said it's not possible to have zero latency in a context switch. The best option at all would be to have more than a group of registers so that all you have to do is to "point" the CPU to the one you want to use with no need of moving data from regs to memory and viceversa.

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Reply to
N1

Dual processors, dual RAM banks, Dual peripherals.

Ed

Reply to
Ed Prochak

This was exactly how it was done in the Texas TMS9900 processor with the register set in RAM. Unfortunately this was done in an era, when microprocessors did not have a fast cache, so the penalty during normal operation was severe, but the context switch was fast :-).

Paul

Reply to
Paul Keinanen

Remember the Z80? One instruction flipped you to the alternate register set (ABCDEHL). IX, IY, SP and PC were unchanged. You had to be sure no idiot used the alternates in the bios, however.

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Reply to
CBFalconer

Two instructions.

08 EX AF,AF' ; AF AF' D9 EXX ; BC/DE/HL BC'/DE'/HL'

- Bill

Reply to
Bill Leary

As you can see from the other answers, this depends largely on the CPU you are using. One exception is a simple Forth system, e.g. a threaded code implementation (

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). Instead of using interrupts, which can have large latencies because of instruction cache flush etc., you could simply execute 100 instructions for each process. Process switching could be done by loading a new instruction pointer for the threaded code and stack pointer. This will be fast on every CPU.

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Reply to
Frank Buss

Perfectly fine, if you only had some miniature system with just two tasks :-).

Paul

Reply to
Paul Keinanen

I wonder why EX AF, AF' was made a distinct instruction?

Some ARMs (at least the ARM7TDMI, the only one I've messed with) have partially banked/shadowed registers--- each of the six processor modes has private copies of two registers (one is used by the hardware to store a return address; the other is typically used as a stack pointer) and the FIQ (fast interrupt) mode has another five general-purpose registers that it doesn't need to save/restore.

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Reply to
Wim Lewis

Which is why ZiLOG opted for a different approach for their Z8 microcontroller - a register pointer, selecting one of the many working register groups in the vast register file (at least, not external RAM like in the TI's case). Fast context switch and awkward program design :(

Stefan

Reply to
Stefan Carter

Good question. I did use EX AF,AF' once to get an alternate accumulator, but I can't remember what I was doing to make that seem like a win. Current versions of that product turned the whole alternate register set over to the big timed interrupt that manages all the hardware polling.

Mel.

Reply to
Mel

Run the two processes on a processor with CMT, chip-multithreading or "hyper-threading", or on a "barrel processor". In a single-pipe CPU, the issue unit will be able to choose an instruction from each thread on a cycle-by-cycle basis. If there are multiple integer pipes, it may be able to schedule instructions from both threads at the same time.

Some network processors (IXP2400) allowed one thread to wake-up a sleeping thread. The sleeping thread could then execute within just a few cycles.

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Reply to
Joseph H Allen

The EX instructions and the alternative registers can be used for more than just a fast context switch. The EX AF,AF' in particular lets you hold two accumulators in the air at a time. It's about twenty years since I last programmed a Z80, so I can't remember any examples.

Reply to
David Brown

By accepting some limitations, there are solutions. As example the Sun Sparc has a huge register set of

256 registers, of which 32 each are for one process. A context switch is as quick as swapping the base pointer, basically one operation. The limitation, there are only 8 processes like that. There might be other architectures that operate like that. I have no idea whether they developped any further.

Rene

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Reply to
Rene Tschaggelar

What I disliked about Z80 is that there is no way to know which set of registers is current. BTW, the ADSP21xx and x51 provide for alternative sets, too.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

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Reply to
Vladimir Vassilevsky

=BF=BDYou had

Isn't that the same as TI?

selecting one of the many working

Some of the 9900 series had internal ram.

Many micro families have multiple register banks

Certainly not very C friendly.

Reply to
cbarn24050

The easiest way to think about it is to assume AF, BC, DE, and HL are always current. Don't try to think that you've swapped over to AF' or BC', DE' and HL'. Instead, think of the EXX instruction as swapping the values between the real registers and the alternative registers.

Reply to
David Brown

In the Z8/eZ8, all registers are/were accumulators - how did the TI handle this?

Reply to
Stefan Carter

The x51 has four register banks, however only one accumulator and only one Xmem pointer register.

Make doing any kind of math a real pain.

Reply to
donald

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